llvm-svn: 132768

No functional change.

Part of PR6965

llvm-svn: 132763

dynamically allocated stack area was not set.

llvm-svn: 132758

llvm-svn: 132756

llvm-svn: 132726

llvm-svn: 132725

- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.

llvm-svn: 132724

llvm-svn: 132718

llvm-svn: 132717

Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue:

- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
  to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
  callee-saved register is emitted even when no callee-saved registers are
  saved.
- When a callee-saved double precision register is saved, two cfi_offset
  directives, one for each of the paired single precision registers, should be
  emitted.
 
 

llvm-svn: 132703

rdar://problem/9556069

llvm-svn: 132699

load.  rdar://problem/6373334

llvm-svn: 132696

rdar://problem/5993888

llvm-svn: 132606

Materializing the stack pointer update before a call requires a scratch
register that may not be available.

llvm-svn: 132601

addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939

llvm-svn: 132561

- Check for MTCTR8 in addition to MTCTR when looking up a hazard.

- When lowering an indirect call use CTR8 when targeting 64bit.

- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.

The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.

llvm-svn: 132552

Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.

rdar://9431157

llvm-svn: 132522

Part of rdar://9119939

llvm-svn: 132510

allocation orders.

llvm-svn: 132509

Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

llvm-svn: 132508

llvm-svn: 132486

llvm-svn: 132479

rdar://problem/6373334

llvm-svn: 132458

No functional change.

llvm-svn: 132455

llvm-svn: 132451

llvm-svn: 132448

llvm-svn: 132444

llvm-svn: 132424

llvm-svn: 132419

floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888

llvm-svn: 132404

Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

llvm-svn: 132398

patch to TargetLowering.cpp.  rdar://problem/5660695

llvm-svn: 132388

llvm-svn: 132355

llvm-svn: 132341

llvm-svn: 132340

llvm-svn: 132336

must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

llvm-svn: 132324

nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323

Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322

directives.

Fixes PR9826.

llvm-svn: 132317