about by icc (#593, partial).  Patch by Erick Tryzelaar.

llvm-svn: 81115

a new class, MachineInstrIndex, which hides arithmetic details from
most clients. This is a step towards allowing the register allocator
to update/insert code during allocation.

llvm-svn: 81040

Fixed a test that ensures the LocalRewriter does not attempt to
avoid reloads by reusing clobbered registers.

This was causing issues in 256.bzip2 when compiled with PIC for
a while (starting at r78217), though the problem has since been masked. 

llvm-svn: 80872

llvm-svn: 79564

llvm-svn: 79397

llvm-svn: 79378

llvm-svn: 78840

llvm-svn: 78667

llvm-svn: 78664

Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg.

llvm-svn: 78620

llvm-svn: 78601

llvm-svn: 78447

New C++ PBQP solver. Currently about as fast (read _slow_) as the old C based solver, but I'll be working to improve that. The PBQP allocator has been updated to use the new solver.

llvm-svn: 78354

llvm-svn: 77754

 - Some clients which used DOUT have moved to DEBUG. We are deprecating the
   "magic" DOUT behavior which avoided calling printing functions when the
   statement was disabled. In addition to being unnecessary magic, it had the
   downside of leaving code in -Asserts builds, and of hiding potentially
   unnecessary computations.

llvm-svn: 77019

llvm-svn: 73634

Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.

llvm-svn: 73346

llvm-svn: 72604

for PostRAScheduler. 

llvm-svn: 71991

llvm-svn: 71057

In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However,  reloads and restores might be folded into uses / defs and freed registers might not be used at all.

VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.

Not yet enabled. This is part 1. More coming.

llvm-svn: 70787

This fixes a very subtle bug. vr defined by an implicit_def is allowed overlap with any register since it doesn't actually modify anything. However, if it's used as a two-address use, its live range can be extended and it can be spilled. The spiller must take care not to emit a reload for the vn number that's defined by the implicit_def. This is both a correctness and performance issue.

llvm-svn: 69743

llvm-svn: 67082

llvm-svn: 66870

Reorganization: Move the Spiller out of VirtRegMap.cpp into its own files.  No (intended) functionality change.

llvm-svn: 66720

llvm-svn: 62600

* Removed trailing whitespace

llvm-svn: 61927

* Removed trailing whitespace

llvm-svn: 61926

llvm-svn: 59629

llvm-svn: 59414

llvm-svn: 59293

instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.

llvm-svn: 57521

llvm-svn: 57018

isReg, etc., from isRegister, etc.

llvm-svn: 57006

Contributed by Lang Hames.

llvm-svn: 56959