works with.

SelectionDAG, FunctionLoweringInfo, and SelectionDAGLowering
objects now get created once per SelectionDAGISel instance, and
can be reused across blocks and across functions. Previously,
they were created and destroyed each time they were needed.

This reorganization simplifies the handling of PHI nodes, and
also SwitchCases, JumpTables, and BitTestBlocks. This
simplification has the side effect of fixing a bug in FastISel
where successor PHI nodes weren't being updated correctly.

This is also a step towards making the transition from FastISel
into and out of SelectionDAG faster, and also making
plain SelectionDAG faster on code with lots of little blocks.

llvm-svn: 55450

llvm-svn: 55439

SSE2 registers as well as the MMX registers.

llvm-svn: 55436

llvm" for consistency.

llvm-svn: 55435

llvm-svn: 55434

llvm-svn: 55433

llvm-svn: 55431

llvm-svn: 55430

Use TargetLowering to get the types in fast isel, which handles pointer types correctly for our purposes.

llvm-svn: 55428

just try to do the action and let the tablegen-generated code
determine if there is target-support for an operation.

llvm-svn: 55427

the details of materializing constants and other values into
registers, and make use of it in several places.

llvm-svn: 55426

llvm-svn: 55425

llvm-svn: 55424

llvm-svn: 55423

64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.

llvm-svn: 55422

of two, and to not need a scratch std::vector. Also, compute the ordering
immediately in the result array, instead of in another scratch std::vector
that is copied to the result array.

llvm-svn: 55421

a scratch std::vector.

llvm-svn: 55420

which isn't needed anymore.

llvm-svn: 55419

verifier. See PR2711 for details.

llvm-svn: 55414

llvm-svn: 55413

llvm-svn: 55409

llvm-svn: 55401

llvm-svn: 55400

llvm-svn: 55399

This simultaneously makes the code simpler and adds support for sext as well.

llvm-svn: 55398

llvm-svn: 55396

llvm-svn: 55394

llvm-svn: 55393

Put a heuristic in place to prevent GVN from falling into bad cases with massively complicated CFGs.
This speeds up a particular testcase from 12+ hours to 5 seconds with little perceptible loss of quality.

llvm-svn: 55391

of two, and to not need a scratch std::vector. Also, use the
SelectionDAG's topological sort in LegalizeDAG instead of having
a separate implementation.

llvm-svn: 55389

llvm-svn: 55387

llvm-svn: 55384

llvm-svn: 55383

llvm-svn: 55381

allowing it to support the full range of conversions people might ask for in a correct manner.

llvm-svn: 55378

llvm-svn: 55377

was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

llvm-svn: 55375

llvm-svn: 55374

llvm-svn: 55373

assign it to a version of the xmm register with the regclass that matches its
type.  This fixes PR2715, a bug handling some crazy xpcom case in mozilla.

llvm-svn: 55358