llvm-svn: 120441

The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function.  Use it
for all the VLD-dup instructions for the sake of consistency.

llvm-svn: 120358

instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333

data. Next up, pseudo-izing them.

llvm-svn: 120320

llvm-svn: 120304

llvm-svn: 120302

llvm-svn: 120298

llvm-svn: 120033

lit.GoogleTest: On case-insensitive filesystem, matching should be case-insensitive when directory name is checked with test_sub_dir.

On MSVS8, ${CMAKE_CFG_INTDIR}, aka $(OutDir), has capitalized name(eg. Debug), although $(OutDir) is made with lower case(eg. debug).

llvm-svn: 119781

Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.

llvm-svn: 119760

llvm-svn: 119759

This makes it symmetric with the 'u' modifier that forces an unsigned type.
This is needed for unsigned vector shifts, where the shift amount still needs
to be signed.  PR8482 (Radar 8603521).

llvm-svn: 119742

and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368

llvm-svn: 119548

instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.

llvm-svn: 119460

llvm-svn: 119406

llvm-svn: 119405

No functional change.

llvm-svn: 119404

Stop defining types with "__neon_" prefixes and then using typedefs without
the prefix; there's no reason to do that anymore.  Remove types that combine
multiple Neon vectors and treat them as a single long vector; they are not
used.

llvm-svn: 119369

I've temporarily disabled the failing clang test.

llvm-svn: 119367

It's breaking buildbots.

llvm-svn: 119363

The system API's will be shifted over to returning an error_code, and returning
other return values as out parameters to the function.

Code that needs to check error conditions will use the errc enum values which
are the same as the posix_errno defines (EBADF, E2BIG, etc...), and are
compatable with the error codes in WinError.h due to some magic in system_error.

An example would be:

if (error_code ec = KillEvil("Java")) { // error_code can be converted to bool.
  handle_error(ec);
}

llvm-svn: 119360

Thanks to Nate Begeman for an earlier version of this patch.

llvm-svn: 119358

'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>

llvm-svn: 119310

llvm-svn: 119130

llvm-svn: 119129

llvm-svn: 119128

Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120

It can pass two tests below on Win32.
  - Clang :: CodeGenCXX/dyncast.cpp
  - LLVM :: CodeGen/ARM/globals.ll

llvm-svn: 119023

llvm-svn: 118829

Add support for specifying a PostEncoderMethod, which can perform post-processing after the automated encoding of an instruction.
Not yet used.

llvm-svn: 118759

their comments.

llvm-svn: 118696

llvm-svn: 118622

llvm-svn: 118359

fixed physical registers.  Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).

llvm-svn: 118352

add fixed immediate values.  Move the aad and aam aliases to
use this, and document it.

llvm-svn: 118350

result instruction operand numbering matched the result pattern.

Fixing this allows us to move the xchg/test aliases to the .td file.

llvm-svn: 118334

from c++ hacks to proper .td InstAlias definitions.  Change them!

llvm-svn: 118330

operand list instead of the operand list redundantly declared on the alias
or instruction.

With this change, we finally remove the ins/outs list on the alias.  Before:
  def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
                  "movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
  def : InstAlias<"movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;

This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.

llvm-svn: 118329

  (someinst GR16:$foo, GR32:$foo)

Reimplement BuildAliasOperandReference to be correctly
based on the names of operands in the result pattern,
instead of on the instruction operand definitions.

llvm-svn: 118328

llvm-svn: 118327