llvm-svn: 85765

Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)

llvm-svn: 85764

llvm-svn: 85746

llvm-svn: 85743

the testcase into:

_test1:                                                     ## @test1
## BB#0:                                                    ## %entry
	leaq	L_test1_bb6(%rip), %rax
	jmpq	*%rax
L_test1_bb:                                                 ## Address Taken
LBB1_1:                                                     ## %bb
	movb	$1, %al
	ret
L_test1_bb6:                                                ## Address Taken
LBB1_2:                                                     ## %bb6
	movb	$2, %al
	ret

Note, it is very very strange that BlockAddressSDNode doesn't carry 
around TargetFlags.  Dan, please fix this.

llvm-svn: 85703

llvm-svn: 85698

them for scalar floating point operations for now.

llvm-svn: 85697

llvm-svn: 85687

llvm-svn: 85685

is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.

llvm-svn: 85675

It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.

llvm-svn: 85643

Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand.  And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.

llvm-svn: 85632

llvm-svn: 85624

unfolding loads for hoisting.  getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.

llvm-svn: 85622

llvm-svn: 85610

void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.

llvm-svn: 85590

clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577

llvm-svn: 85557

llvm-svn: 85546

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517

realignment regardless of whether it's strictly necessary.

llvm-svn: 85476

I'm going to redo this using the OptimizeForSize function attribute.

llvm-svn: 85426

opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411

llvm-svn: 85410

llvm-svn: 85406

llvm-svn: 85381

llvm-svn: 85379

In the new world order, BlockAddress can have a BasicBlock operand.
This doesn't permute much, because if you have a ConstantExpr (or
anything more specific than Constant) we still know the operand has
to be a Constant.

llvm-svn: 85375

llvm-svn: 85362

llvm-svn: 85361

eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.

This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.

llvm-svn: 85357

llvm-svn: 85355

llvm-svn: 85351

use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.

llvm-svn: 85346

llvm-svn: 85341

llvm-svn: 85335

llvm-svn: 85334

default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.

llvm-svn: 85333

llvm-svn: 85332

llvm-svn: 85331