allocator. Fixes PR13945.

llvm-svn: 165201

llvm-svn: 165200

macro instruction (li) in the assembler.

We have identified three possible expansions depending on 
the size of immediate operand:
  1) for 0 ≤ j ≤ 65535.
     li d,j =>
     ori d,$zero,j

  2) for −32768 ≤ j < 0.
     li d,j =>
     addiu d,$zero,j

  3) for any other value of j that is representable as a 32-bit integer.
     li d,j =>
     lui d,hi16(j)
     ori d,d,lo16(j)

All of the above have been implemented in ths patch.

Contributer: Vladimir Medic
llvm-svn: 165199

llvm-svn: 165198

up being contracted during codegen.

llvm-svn: 165197

llvm-svn: 165196

mess by handling all pragmas which the parser touches uniformly.
<rdar://problem/12248901>, etc.

llvm-svn: 165195

This patch is a partial implementation of mips .set assembler directive. Directive is defined as follows:
.set option
The patch implements following options

    at - lets the assembler use the $at register for macros,
         but generates warnings if the source program uses $at

    noat - let source programs use $at without issuingwarnings.

    noreorder - prevents the assembler from reordering machine 
                language instructions.
    nomacro - causes the assembler to print a warning whenever 
              an assembler operation generates more than one 
              machine language instruction.
    macro - lets the assembler generate multiple machine instructions 
            from a single assembler instruction
    reorder - lets the assembler reorder machine language 
               instructions to improve performance

The above variants are parsed and their boolean values set or unset.
The code to actually use them will come later.

Following options are not implemented yet:

nomips16
nomicromips
move
nomove

Contributer: Vladimir Medic
llvm-svn: 165194

ProcessGDBRemote and DynamicLoaderDarwinKernel and a patch was needed
to get this building on Linux.  Thanks!

llvm-svn: 165193

llvm-svn: 165192

/Users/void/llvm/llvm-tot.src/projects/compiler-rt/lib/arm/eqdf2vfp.S:22:2: error: instruction requires: VFP2
 vmov d6, r0, r1
 ^
/Users/void/llvm/llvm-tot.src/projects/compiler-rt/lib/arm/eqdf2vfp.S:23:2: error: instruction requires: VFP2
 vmov d7, r2, r3
 ^
/Users/void/llvm/llvm-tot.src/projects/compiler-rt/lib/arm/eqdf2vfp.S:24:2: error: instruction requires: VFP2
 vcmp.f64 d6, d7
 ^
/Users/void/llvm/llvm-tot.src/projects/compiler-rt/lib/arm/eqdf2vfp.S:25:2: error: instruction requires: VFP2
 vmrs apsr_nzcv, fpscr
 ^

llvm-svn: 165191

llvm-svn: 165190

When aliasing tools, rather than using the base TOOLEXENAME, we should
instead use the built tool's basename (for 'make') or the installed
tool's basename (for 'make install').

This should not cause any changes for anyone building unprefixed 'clang'
and 'clang++' tools.

Patch by Rick Foos!

llvm-svn: 165189

llvm-svn: 165188

llvm-svn: 165187

llvm-svn: 165186

file name if building Apple-style.

llvm-svn: 165185

file name if building Apple-style.

llvm-svn: 165184

llvm-svn: 165182

Removed architecture dependent .sbss section creation.

Updated test case to show the change in section types and removal of a sbss section.

llvm-svn: 165181

This allows the processor-specific machine model to override selected
base opcodes without any fanciness.
e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>.

llvm-svn: 165180

A processor can now arbitrarily alias one SchedWrite onto
another. Only the SchedAlias definition need be within the processor
model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or
transitively refer to another alias.

llvm-svn: 165179

llvm-svn: 165178

llvm-svn: 165177

llvm-svn: 165176

llvm-svn: 165175

MSVC compiler.

llvm-svn: 165174

in the Intel syntax.

The MC layer supports emitting in the Intel syntax, but this would require the
inline assembly MachineInstr to be lowered to an MCInst before emission.  This
is potential future work, but for now emitting directly from the MachineInstr
suffices.

llvm-svn: 165173

for the number of bytes in a particular instruction
to using
   const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
   Desc.getSize()

This is necessary with the advent of 16 bit instructions with
mips16 and micromips. It is also puts Mips in compliance with
the other targets for getting instruction size.

llvm-svn: 165171

  * Return correct size and alignment for common symbols.

llvm-svn: 165170

<rdar://problem/12408181> Fixing a bug where we would try to look for types in a module, and then fail to look for them anywhere else because the same SymbolContext was being passed everywhere

llvm-svn: 165169

llvm-svn: 165168

llvm-svn: 165167

llvm-svn: 165166

In order to avoid rev-lock with Clang when moving to the new API, also
preserve the current API temporarily and insert a shim to implement the
new API in terms of the old.

llvm-svn: 165165

llvm-svn: 165164

llvm-svn: 165163

llvm-svn: 165162

llvm-svn: 165161

imports via ImportDecls.

llvm-svn: 165160