adjustment.  If so, we merge the adjustment into the existing one.  This
allows us to generate:

caller2:
        sub %ESP, 12
        mov DWORD PTR [%ESP], 0
        mov %EAX, 1234567890
        mov %EDX, 0
        call func2
        add %ESP, 8
        ret 4

intead of:

caller2:
        sub %ESP, 12
        mov DWORD PTR [%ESP], 0
        mov %EAX, 1234567890
        mov %EDX, 0
        call func2
        sub %ESP, 4
        add %ESP, 12
        ret 4

for X86/fast-cc-merge-stack-adj.ll

llvm-svn: 22038

llvm-svn: 22036

This fixes fourinarow with -enable-x86-fastcc.

llvm-svn: 22022

to do ugly hackery to avoid emitting code like this:

   call foo
   mov vreg, EAX
   adjcallstackup ...

If foo is a fastcc call and if vreg gets spilled, we might end up with this:

   call foo
   mov [ESP+offset], EAX     ;; Offset doesn't consider the 12!
   sub ESP, 12

Which is bad.  The previous hacky code to deal with this was A) gross B) not
good enough.  In particular, it could miss cases and emit the bad code above.
Now we always emit this:

   call foo
   adjcallstackup ...
   mov vreg, EAX

directly.

This makes fastcc with callees poping the stack work much better.  Next
stop (finally!) really is tail calls.

llvm-svn: 22021

This should fix some missing symbols problems on BSD and improve performance
of programs that use that operation.

llvm-svn: 22012

is always 8-byte aligned for fastcc

llvm-svn: 21995

llvm-svn: 21991

llvm-svn: 21988

llvm-svn: 21986

llvm-svn: 21985

do not use

llvm-svn: 21984

llvm-svn: 21980

llvm-svn: 21977

llvm-svn: 21976

llvm-svn: 21962

llvm-svn: 21960

llvm-svn: 21959

llvm-svn: 21958

llvm-svn: 21945

llvm-svn: 21939

each live in, and copy the regs from the vregs.  As the very first thing we
do in the function, insert copies from the pregs to the vregs.  This fixes
problems where the token chain of CopyFromReg was not enough to allow reordering
of the copyfromreg nodes and other unchained nodes (e.g. div, which clobbers
eax on intel).

llvm-svn: 21932

llvm-svn: 21915

two integer values in registers for the fastcc calling conv.

llvm-svn: 21912

llvm-svn: 21899

llvm-svn: 21898

llvm-svn: 21884

1. Teach LegalizeDAG how to better legalize CTTZ if the target doesn't have
   CTPOP, but does have CTLZ
2. Teach PPC32 how to do sub x, const -> add x, -const for valid consts
3. Teach PPC32 how to do and (xor a, -1) b -> andc b, a
4. Teach PPC32 that ISD::CTLZ -> PPC::CNTLZW

llvm-svn: 21880

llvm-svn: 21878

llvm-svn: 21877

instructions.
Review of this commit would be greatly appreciated.

llvm-svn: 21876

the primary user of this will probably end up being find-first-set-bit/find-
last-set-bit, which i'll get around to...

llvm-svn: 21860

llvm-svn: 21858

llvm-svn: 21857

llvm-svn: 21840

llvm-svn: 21838

that were failing with the pattern selector.  Note that the support that
existed in the simple selector was clearly broken in several ways though
(which has also been fixed).

llvm-svn: 21831

llvm-svn: 21830

llvm-svn: 21829

the pattern isel.

llvm-svn: 21828

uint

llvm-svn: 21821