llvm-svn: 189580

There are several optional (off-by-default) features in CodeGen that can make
use of alias analysis. These features are important for generating code for
some kinds of cores (for example the (in-order) PPC A2 core). This adds a
useAA() function to TargetSubtargetInfo to allow these features to be enabled
by default on a per-subtarget basis.

Here is the first use of this function: To control the default of the
-enable-aa-sched-mi feature.

llvm-svn: 189563

32-bit absolute addressing in instructions likei this:

	mov $_f, %rsi

which is not supported in 64-bit mode.

rdar://8827134

llvm-svn: 189543

Fix a few things in one swoop.

# Add some negative tests.
# Fix some formatting issues.
# Add some missing IsThumb / ARMv8
# Fix some outs / ins mistakes.

llvm-svn: 189490

The usual default of "dmb ish" (inner-shareable) isn't even a valid instruction
on v6M or v7M (well, it does the same thing but software is strongly
discouraged from using it) so we should emit a full-system barrier there.

llvm-svn: 189483

llvm-svn: 189482

Clang is now generating cleaner IR, so this removes the old variants which
should be completely unused.

llvm-svn: 189481

The vqdmlal and vqdmlls instructions are really just a fused pair consisting of
a vqdmull.sN and a vqadd.sN. This adds patterns to LLVM so that we can switch
Clang's CodeGen over to generating these instead of the special vqdmlal
intrinsics.

llvm-svn: 189480

These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.

Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.

llvm-svn: 189478

llvm-svn: 189476

llvm-svn: 189472

llvm-svn: 189471

For now just handles simple comparisons of an ANDed value with zero.
The CC value provides enough information to do any comparison for a
2-bit mask, and some nonzero comparisons with more populated masks,
but that's all future work.

llvm-svn: 189469

The MSA control registers have been added as reserved registers,
and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered
into these nodes.

llvm-svn: 189468

[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri

llvm-svn: 189467

This uses the infrastructure added for memcpy and memmove in r189331.

llvm-svn: 189458

llvm-svn: 189456

in use supports it.

llvm-svn: 189439

For now, (defined(X86_64_JIT) && defined(__CYGWIN__)) satisfies Cygwin64.

llvm-svn: 189437

In the LLVM side, x86_64-cygwin is almost as same as x86_64-mingw32.

llvm-svn: 189436

Also, fix predicates.

llvm-svn: 189432

No functionality change.

llvm-svn: 189431

llvm-svn: 189430

Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20'

Reviewers: craig.topper, rnk

Reviewed By: rnk

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1470

llvm-svn: 189407

first. Use this to turn the PPC modifiers into PPC specific expressions,
allowing them to work on constants.

llvm-svn: 189400

llvm-svn: 189396

llvm-svn: 189388

llvm-svn: 189349

Fix two issues I found while writing these tests.

llvm-svn: 189341

These instructions aren't particularly complicated and it's well worth having
patterns for some reasonably useful LLVM IR that will match them. Soon we
should be able to switch Clang over to producing this natural version.

llvm-svn: 189335

llvm-svn: 189332

Lengths up to a certain threshold (currently 6 * 256) use a series of MVCs.
Lengths above that threshold use a loop to handle X*256 bytes followed
by a single MVC to handle the excess (if any).  This loop will also be
needed in future when support for variable lengths is added.

Because the same tablegen classes are used to define MVC and CLC,
the patch also has the side-effect of defining a pseudo loop instruction
for CLC.  That instruction isn't used yet (and wouldn't be handled correctly
if it were).  I'm planning to use it soon though.

llvm-svn: 189331

llvm-svn: 189330

llvm-svn: 189326

Revert "Fix the build broken by r189315." and "Move everything depending on Object/MachOFormat.h over to Support/MachO.h."

This reverts commits r189319 and r189315. r189315 broke some tests on what I
believe are big-endian platforms.

llvm-svn: 189321

llvm-svn: 189315

Get the register class right for the TST instruction. This keeps the
machine verifier happy, enabling us to turn it on for another test.

rdar://12594152

llvm-svn: 189274

llvm-svn: 189272

Constant pool and global value reference instructions need more
restricted register classes than plain GPR.

rdar://12594152

llvm-svn: 189270

The create machine code wasn't properly in SSA, which the machine verifier
properly complains about. Now that fast-isel is closer to verifier clean,
errors like this show up more clearly.

Additionally, the Thumb pseudo tPICADD was used for both ARM and Thumb
mode functions, which is obviously wrong. Fix that along the way.

Test case is part of the following commit which will finish making an
additional fast-isel test verifier clean an enable it for the
regression test suite. This commit is separate since its not just
a verifier cleanup, but an actual correctness issue.

rdar://12594152 (for the fast-isel verifier aspects)

llvm-svn: 189269