Original commit message:
    Allow up to 64 functional units per processor itinerary.

    This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
    This will be needed for some upcoming PowerPC itineraries.

llvm-svn: 159027

llvm-svn: 159026

there. I didn't notice this because I had a stub that wasn't checked in
floating around in my client.

llvm-svn: 159025

EmitZerofill should take a 64-bit size or else it's chopping off large zero-filled global. rdar://11729134

llvm-svn: 159023

Don't try to print out the live range of a physreg.

llvm-svn: 159021

DBG_VALUE instructions could be referring to non-existing virtual
registers.

llvm-svn: 159020

There is no need to check for physreg live ranges. They don't exist any
more.

llvm-svn: 159019

Everyone is using on-demand regunit ranges now.

llvm-svn: 159018

llvm-svn: 159017

revert CodeGen support for the alloc_size attribute until we finish the design of a more generic metadata node

llvm-svn: 159016

These functions only operate on virtual registers now, and they all have
live ranges.

llvm-svn: 159015

llvm-svn: 159014

Don't depend on LiveIntervals::hasInterval() to determine if a physreg
is reserved and constant.

llvm-svn: 159013

llvm-svn: 159012

llvm-svn: 159011

We don't handle exceptions yet, so we treat them as sinks. ExprEngine
hardcodes messages that are known to raise Objective-C exceptions like -raise,
but it was only checking for +raise:format: and +raise:format:arguments: on
NSException itself, not subclasses.

<rdar://problem/11724201>

llvm-svn: 159010

This should produce the same results as using physreg liveness directly.

llvm-svn: 159009

properly if there is a join point in the control flow graph that involves
a trylock.  Also changes the source locations of some warnings to be
more consistent.

llvm-svn: 159008

llvm-svn: 159007

With regunit liveness permanently enabled, this function would always
return true.

Also remove now obsolete code for checking physreg interference.

llvm-svn: 159006

when the calling site is a member function template.

Effectively reverts r111675.

llvm-svn: 159004

This fixes PR5997.

These transforms were disabled because codegen couldn't deal with other
uses of trunc(x). This is now handled by the peephole pass.

This causes no regressions on x86-64.

llvm-svn: 159003

llvm-svn: 159002

llvm-svn: 159001

llvm-svn: 159000

llvm-svn: 158999

not a pointer to a fast-enumerable object. // rdar://11488666

llvm-svn: 158998

Original message:
Performance optimizations:
- SwitchInst: case values stored separately from Operands List. It allows to make faster access to individual case value numbers or ranges.
- Optimized IntItem, added APInt value caching.
- Optimized IntegersSubsetGeneric: added optimizations for cases when subset is single number or when subset consists from single numbers only.

llvm-svn: 158997

Allow divsi3 to take advantage of a hardware unsigned divide when it is available, by replacing an explicit call to udivsi3 with the divide operator.  Patch by Sébastien Bourdeauducq.

llvm-svn: 158996

llvm-svn: 158995

llvm-svn: 158994

knows dwarf or not.

llvm-svn: 158993

DwarfUsesRelocationsAcrossSections.

llvm-svn: 158992

llvm-svn: 158991

llvm-svn: 158989

This improves signal-/fork-safety of instrumented programs.

llvm-svn: 158988

llvm-svn: 158987

fail.  Original commit message:

Performance optimizations:
- SwitchInst: case values stored separately from Operands List. It allows to make faster access to individual case value numbers or ranges.
- Optimized IntItem, added APInt value caching.
- Optimized IntegersSubsetGeneric: added optimizations for cases when subset is single number or when subset consists from single numbers only.

On my machine these optimizations gave about 4-6% of compile-time improvement.

llvm-svn: 158986

llvm-svn: 158985

llvm-svn: 158982