llvm-svn: 127982

Re-apply r127953 with fixes: eliminate empty return block if it has no predecessors; update dominator tree if cfg is modified.

llvm-svn: 127981

llvm-svn: 127976

llvm-svn: 127975

llvm-svn: 127974

llvm-svn: 127973

gun as does. This makes it a lot easier to compare the output of both
as the addresses are now a lot closer.

llvm-svn: 127972

Add an optimization to GlobalOpt that eliminates calls to __cxa_atexit, if the function passed is empty.

llvm-svn: 127970

- glibc falls back to fork+exec if a file actions object is present.
- On BSDs this saves a malloc.

llvm-svn: 127969

If a class inherits from RefCountedBaseVPTR allow all its subclasses to be used with IntrusiveRefCntPtr.

llvm-svn: 127966

This can happen when multiple sibling registers are spilled after live range
splitting.

llvm-svn: 127965

llvm-svn: 127964

llvm-svn: 127962

llvm-svn: 127960

llvm-svn: 127959

Some of those POSIX <-> Windows command line conversions ended on
failure.

llvm-svn: 127958

llvm-svn: 127957

llvm-svn: 127956

to canonicalize IR", it broke a lot of things.

llvm-svn: 127954

to have single return block (at least getting there) for optimizations. This
is general goodness but it would prevent some tailcall optimizations.
One specific case is code like this:
int f1(void);
int f2(void);
int f3(void);
int f4(void);
int f5(void);
int f6(void);
int foo(int x) {
  switch(x) {
  case 1: return f1();
  case 2: return f2();
  case 3: return f3();
  case 4: return f4();
  case 5: return f5();
  case 6: return f6();
  }
}

=>
LBB0_2:                                 ## %sw.bb
  callq   _f1
  popq    %rbp
  ret
LBB0_3:                                 ## %sw.bb1
  callq   _f2
  popq    %rbp
  ret
LBB0_4:                                 ## %sw.bb3
  callq   _f3
  popq    %rbp
  ret

This patch teaches codegenprep to duplicate returns when the return value
is a phi and where the phi operands are produced by tail calls followed by
an unconditional branch:

sw.bb7:                                           ; preds = %entry
  %call8 = tail call i32 @f5() nounwind
  br label %return
sw.bb9:                                           ; preds = %entry
  %call10 = tail call i32 @f6() nounwind
  br label %return
return:
  %retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ]
  ret i32 %retval.0

This allows codegen to generate better code like this:

LBB0_2:                                 ## %sw.bb
        jmp     _f1                     ## TAILCALL
LBB0_3:                                 ## %sw.bb1
        jmp     _f2                     ## TAILCALL
LBB0_4:                                 ## %sw.bb3
        jmp     _f3                     ## TAILCALL

rdar://9147433

llvm-svn: 127953

llvm-svn: 127952

not have native support for this operation (such as X86).
The legalized code uses two vector INT_TO_FP operations and is faster
than scalarizing.

llvm-svn: 127951

llvm-svn: 127948

description updates.

llvm-svn: 127947

update short descriptions to match those from the options, alphabetize table
of contents.

llvm-svn: 127946

llvm-svn: 127945

llvm-svn: 127944

llvm-svn: 127943

llvm-svn: 127941

llvm-svn: 127939

The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand.  Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.

llvm-svn: 127935

Tweak CrashRecoveryContextCleanup to provide an easy method for clients to select between 'delete' and 'destructor' cleanups, and allow the destructor of CrashRecoveryContextCleanupRegister to be pseudo re-entrant.

llvm-svn: 127929

Tweak CrashRecoveryContext::GetCurrent() to return quickly if 'gCrsahRecoveryEnabled' is false.  This avoids us needing to go to thread local storage for
the performance sensitive case where we are compiling code.

llvm-svn: 127928

(one-by-one until valgrind is happy)

llvm-svn: 127925

If an AllocaInst referred by DbgDeclareInst is used by a LoadInst then the LoadInst should also get a corresponding llvm.dbg.value intrinsic.

llvm-svn: 127924

llvm-svn: 127923

llvm-svn: 127922

llvm-svn: 127918

Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD.  More work left to be done to support other instances of shifter ops in the ISA.

llvm-svn: 127917

Proof-of-concept code that code-gens a module to an in-memory MachO object.
This will be hooked up to a run-time dynamic linker library (see: llvm-rtdyld
for similarly conceptual work for that part) which will take the compiled
object and link it together with the rest of the system, providing back to the
JIT a table of available symbols which will be used to respond to the
getPointerTo*() queries.

llvm-svn: 127916