llvm-svn: 86340

  except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.

llvm-svn: 86328

Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers.  Coming soon, code to perform sret-demotion if return values cannot be lowered to registers

llvm-svn: 86324

A non-identity copy cannot be coalesced when the phi join destination register
is live at the copy site.

Also verify the condition that the PHI join source register is only used in
the PHI join. Otherwise the coalescing is invalid.

llvm-svn: 86322

llvm-svn: 86295

prints them with the leading '@'.

llvm-svn: 86261

llvm-svn: 86259

llvm-svn: 86212

llvm-svn: 86199

problems with name collisions.

llvm-svn: 86189

Added support for renumbering existing index list elements. Removed some junk from the initial numbering code in runOnMachineFunction.

llvm-svn: 86184

Fix bug in aggressive antidep breaking; liveness was not updated correctly for regions that do not have antidep candidates.

llvm-svn: 86172

llvm-svn: 86151

llvm-svn: 86102

Break anti-dependencies using free registers in a round-robin manner to avoid introducing new anti-dependencies.

llvm-svn: 86098

llvm-svn: 86092

llvm-svn: 86085

llvm-svn: 86080

While calculating original type size for a derived type, handle type variants encoded as DIDerivedType appropriately.
This improves bitfield support.

llvm-svn: 86073

Fix DW_AT_data_member_location for bit-fields. It points to the location of annonymous field that covers respective field.

llvm-svn: 86054

Handle empty/tombstone keys for LiveIndex more cleanly. Check for index sanity when constructing index list entries.

llvm-svn: 86049

llvm-svn: 86044

llvm-svn: 86043

The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output.

With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF.

llvm-svn: 86041

and extract_subreg as a "copy" that defines a valno.
Also fixes a typo. These two issues prevent a simple subreg coalescing from
happening before.

llvm-svn: 86022

llvm-svn: 85994

This introduces a new pass, SlotIndexes, which is responsible for numbering
instructions for register allocation (and other clients). SlotIndexes numbering
is designed to match the existing scheme, so this patch should not cause any
changes in the generated code.

For consistency, and to avoid naming confusion, LiveIndex has been renamed
SlotIndex.

The processImplicitDefs method of the LiveIntervals analysis has been moved
into its own pass so that it can be run prior to SlotIndexes. This was
necessary to match the existing numbering scheme.

llvm-svn: 85979

an unconditional branch (possibly from tail merging), this code is
trying to redirect all of its predecessors to go directly to the branch
target, but that isn't feasible for indirect branches.  The other
predecessors (that don't end with indirect branches) could theoretically
still be handled, but that is not easily done right now.

The AnalyzeBranch interface doesn't currently let us distinguish jump table
branches from indirect branches, and this code is currently handling
jump tables.  To avoid punting on address-taken blocks, we would have to give
up handling jump tables.  That seems like a bad tradeoff.

llvm-svn: 85975

llvm-svn: 85947

Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed.

llvm-svn: 85939

<rdar://problem/7352605>. When building schedule graph use mayAlias information to avoid chaining loads/stores of spill slots with non-aliased memory ops.

llvm-svn: 85934

llvm-svn: 85909

warning from gcc by removing VISIBILITY_HIDDEN attributes.  

llvm-svn: 85873

llvm-svn: 85827

Chain dependencies used to enforce memory order should have latency of 0 (except for true dependency of Store followed by aliased Load... we estimate that case with a single cycle of latency assuming the hardware will bypass)

llvm-svn: 85807

the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.

llvm-svn: 85799

llvm-svn: 85762

llvm-svn: 85684

 - Be consistent when referring to MachineBasicBlocks: BB#0.
 - Be consistent when referring to virtual registers: %reg1024.
 - Be consistent when referring to unknown physical registers: %physreg10.
 - Be consistent when referring to known physical registers: %RAX
 - Be consistent when referring to register 0: %reg0
 - Be consistent when printing alignments: align=16
 - Print jump table contents.
 - Don't print host addresses, in general.
 - and various other cleanups.

llvm-svn: 85682

previously running CodePlacementOpt. Also print headers before
each dump in -print-machineinstrs mode, so that it's clear which
dump is which.

llvm-svn: 85681