- Remove code which lowers pseudo SETGP01.
- Fix LowerSETGP01. The first two of the three instructions that are emitted to
  initialize the global pointer register now use register $2.
- Stop emitting .cpload directive.

llvm-svn: 156689

llvm-svn: 156687

Empty live ranges represent undef and still get allocated, but they
won't appear in LiveIntervalUnions.

Patch by Patrik Hägglund!

llvm-svn: 156685

pointer register. 


This is the first of the series of patches which clean up the way global pointer
register is used. The patches will make the following improvements:

- Make $gp an allocatable temporary register rather than reserving it.
- Use a virtual register as the global pointer register and let the register
  allocator decide which register to assign to it or whether spill/reloads are
  needed.
- Make sure $gp is valid at the entry of a called function, which is necessary
  for functions using lazy binding.
- Remove the need for emitting .cprestore and .cpload directives.

llvm-svn: 156671

llvm-svn: 156665

llvm-svn: 156663

llvm-svn: 156662

llvm-svn: 156658

llvm-svn: 156656

llvm-svn: 156655

llvm-svn: 156652

llvm-svn: 156649

llvm-svn: 156648

llvm-svn: 156646

llvm-svn: 156644

llvm-svn: 156636

llvm-svn: 156635

Patch by Jyotsna Verma.

llvm-svn: 156634

llvm-svn: 156633

llvm-svn: 156632

llvm-svn: 156631

Don't compute the SuperRegs list until the sub-register graph is
completely finished. This guarantees that the list of super-registers is
properly topologically ordered, and has no duplicates.

llvm-svn: 156629

retval.  Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796

llvm-svn: 156628

llvm-svn: 156625

to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796

llvm-svn: 156622

llvm-svn: 156621

llvm-svn: 156620

llvm-svn: 156615

llvm-svn: 156613

llvm-svn: 156612

This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).

llvm-svn: 156611

Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.

llvm-svn: 156609

Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.

llvm-svn: 156608

llvm-svn: 156606

llvm-svn: 156603

llvm-svn: 156602

llvm-svn: 156601

llvm-svn: 156600

This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411
llvm-svn: 156599

but it generates int3 on x86 instead of ud2.

llvm-svn: 156593