llvm-svn: 186811

llvm-svn: 186809

llvm-svn: 186787

llvm-svn: 186566

llvm-svn: 186496

Make x86 fast-isel correctly choose between aligned and unaligned operations for vector stores. Fixes PR16640.

llvm-svn: 186491

Use PMIN/PMAX for UGE/ULE vector comparions to reduce the number of required
instructions. This trick also works for UGT/ULT, but there is no advantage in
doing so. It wouldn't reduce the number of instructions and it would actually
reduce performance.

Reviewer: Ben

radar:5972691

llvm-svn: 186432

llvm-svn: 186308

llvm-svn: 186274

radar://14351991

llvm-svn: 186189

In particular:
movsbw %al, %ax   --> cbtw
movswl %ax, %eax  --> cwtl
movslq %eax, %rax --> cltq

According to Intel's manual those have the same performance characteristics but
come with a smaller encoding.

llvm-svn: 186174

Patch by Andrea Di Biagio

llvm-svn: 186165

Summary:
This patch adds explicit calling convention types for the Win64 and
System V/x86-64 ABIs. This allows code to override the default, and use
the Win64 convention on a target that wants to use SysV (and
vice-versa). This is needed to implement the `ms_abi` and `sysv_abi` GNU
attributes.

Reviewers:

CC:

llvm-svn: 186144

in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:

1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.

2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.

3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.

The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.

llvm-svn: 185956

llvm-svn: 185900

Explicit references to %AH for an i8 remainder instruction can lead to
references to %AH in a REX prefixed instruction, which causes things to
blow up. Do the same thing in FastISel as we do for DAG isel and instead
shift %AX right by 8 bits and then extract the 8-bit subreg from that
result.

rdar://14203849
http://llvm.org/bugs/show_bug.cgi?id=16105

llvm-svn: 185899

Reapply this as I reverted the wrong commit.

llvm-svn: 185807

This reverts commit 2b52880592a525cfe04d8f9008a35da8c2ea94c3.

Needs review.

llvm-svn: 185806

This reverts commit 01f8d579f7672872324208ac5bc4ac311e81b22e.

llvm-svn: 185781

llvm-svn: 185778

llvm-svn: 185763

These exception-related opcodes are not used any longer.

llvm-svn: 185625

Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."

llvm-svn: 185600

These exception-related opcodes are not used any longer.

llvm-svn: 185596

Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.

llvm-svn: 185540

[DebugInfo] Allow getDebugThreadLocalSymbol to return MCExpr

This allows getDebugThreadLocalSymbol to return a generic MCExpr
instead of just a MCSymbolRefExpr.

This is in preparation for supporting debug info for TLS variables
on PowerPC, where we need to describe the variable location using
a more complex expression than just MCSymbolRefExpr.

llvm-svn: 185460

Restrict the current TLS support to X86 ELF for now. Test that we don't
produce it on PPC & we can flesh that test case out with the right thing
once someone implements it.

llvm-svn: 185389

llvm-svn: 185292

is trying to do.

llvm-svn: 185191

llvm-svn: 185131

llvm-svn: 185086

CostModel: improve the cost model for load/store of non power-of-two types such as <3 x float>, which are popular in graphics.

llvm-svn: 185085

llvm-svn: 185071

Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector.

llvm-svn: 184931

radar://14057959

llvm-svn: 184872

This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c.

llvm-svn: 184823

Sorry for the unit test churn. I'll try to make the change permanently
next time.

llvm-svn: 184705

This is an awful implementation of the target hook. But we don't have
abstractions yet for common machine ops, and I don't see any quick way
to make it table-driven.

llvm-svn: 184664

llvm-svn: 184642

A FastISel optimization was causing us to emit no information for such
parameters & when they go missing we end up emitting a different
function type. By avoiding that shortcut we not only get types correct
(very important) but also location information (handy) - even if it's
only live at the start of a function & may be clobbered later.

Reviewed/discussion by Evan Cheng & Dan Gohman.

llvm-svn: 184604