llvm-svn: 107615

the example in the testcase, we now generate:

_test1:                                 ## @test1
	movss	4(%esp), %xmm0
	addss	8(%esp), %xmm0
	movl	12(%esp), %eax
	movss	%xmm0, (%eax)
	ret

instead of:

_test1:                                                     ## @test1
	subl	$20, %esp
	movl	24(%esp), %eax
	movq	%mm0, (%esp)
	movq	%mm0, 8(%esp)
	movss	(%esp), %xmm0
	addss	12(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$20, %esp
	ret

v2f32 support did not work reliably because most of the X86
backend didn't know it was legal.  It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode.  If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32.  However,
we generally don't try very hard to be abi compatible on gcc
extended vectors. 

llvm-svn: 107601

v2f32 as legal in 32-bit mode.  It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.

llvm-svn: 107600

Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.

llvm-svn: 107550

llvm-svn: 107280

llvm-svn: 107130

llvm-svn: 107067

llvm-svn: 106944

for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.

llvm-svn: 106893

- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.

llvm-svn: 106880

address requires a register or secondary load to compute
(most PIC modes).  This improves "g" constraint handling.  8015842.

The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously.  Fixed to use Linux x86-64.

llvm-svn: 106779

llvm-svn: 106746

bt instruction, which was exposed by r106263.

llvm-svn: 106718

Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.

llvm-svn: 106634

to using that.

llvm-svn: 106633

Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang.

Conflicts:

	lib/CodeGen/MachineSink.cpp

llvm-svn: 106614

llvm-svn: 106574

llvm-svn: 106405

SDNode *, since it doesn't care about the ResNo value.

llvm-svn: 106282

llvm-svn: 106280

llvm-svn: 106279

llvm-svn: 106278

which is faster, simpler, and less surprising.

llvm-svn: 106263

will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.

llvm-svn: 106066

a relative address.

llvm-svn: 106064

the register.  While we're at it, make sure it's in the right one.

llvm-svn: 105645

I don't think this ever resulted in problems on x86, but it
would on ARM.

llvm-svn: 105509

llvm-svn: 105381

backend.  Add a FIXME noting what can be fixed here.

llvm-svn: 105342

mailing list archives.

llvm-svn: 105341

x86 backend currently doesn't know how to handle them.

This doesn't really fix anything because LegalizeTypes doesn't know how to
handle them either.  We do get a better error message, though.

llvm-svn: 105305

Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments.

llvm-svn: 105092

llvm-svn: 105059

No functional effect as these nodes are not generated yet.

llvm-svn: 104879

To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.

llvm-svn: 104866

llvm-svn: 104691

llvm-svn: 104421

llvm-svn: 104337

Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.

llvm-svn: 104336

tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.

llvm-svn: 104308