Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467

llvm-svn: 128977

llvm-svn: 128974

Start teaching the runtime Dyld interface to use the memory manager API
for allocating space. Rather than mapping directly into the MachO object,
we extract the payload for each object and copy it into a dedicated buffer
allocated via the memory manager. For now, just do Segment64, so this works
on x86_64, but not yet on ARM.

llvm-svn: 128973

llvm-svn: 128970

llvm-svn: 128969

llvm-svn: 128968

Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.

llvm-svn: 128965

llvm-svn: 128964

llvm-svn: 128963

llvm-svn: 128962

Treat the landing pad as a normal successor when that happens.

llvm-svn: 128961

llvm-svn: 128959

encodings for DisassembleArithMiscFrm().

rdar://problem/9238659

llvm-svn: 128958

llvm-svn: 128955

it already is.

llvm-svn: 128954

llvm-svn: 128953

this class. Clang was warning on this with -Wnon-virtual-dtor.

llvm-svn: 128952

llvm-svn: 128951

    Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445

llvm-svn: 128949

llvm-svn: 128947

llvm-svn: 128946

Added checks for regs which should not be 15.

rdar://problem/9237734

llvm-svn: 128945

still used by RegionInfo :(

llvm-svn: 128943

It would be better to browse without stylesheet. (eg. on ViewVC)

llvm-svn: 128942

For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693

llvm-svn: 128941

Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.

llvm-svn: 128940

llvm-svn: 128938

llvm-svn: 128936

llvm-svn: 128935

llvm-svn: 128933

llvm-svn: 128929

llvm-svn: 128927

of a basic block.

llvm-svn: 128925

llvm-svn: 128924

Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.

rdar://problem/9236873

llvm-svn: 128922

llvm-svn: 128920

llvm-svn: 128919

When dead code elimination removes all but one use, try to fold the single def into the remaining use.

Rematerialization can leave single-use loads behind that we might as well fold whenever possible.

llvm-svn: 128918

llvm-svn: 128914

llvm-svn: 128913