example, this:

(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))

is ambiguous because DPR contains both f64 and v2f32.  tblgen
currently accidentally picks f64 because it's first in the 
regclass.

llvm-svn: 97955

llvm-svn: 97348

A8.6.297

llvm-svn: 95885

A8.6.335 & A8.6.336

llvm-svn: 95703

For disassembly only.

A8.6.300

llvm-svn: 95669

The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.

A8.6.295

llvm-svn: 95584

llvm-svn: 95560

A8.6.331 VMOV (between two ARM core registers and two single-precision registers)

llvm-svn: 95548

llvm-svn: 95397

bit (Inst{22}) and the M bit (Inst{5}) should be left unspecified.  For binary
format instructions, Inst{6} and Inst{4} need to specified for proper decodings.

llvm-svn: 94855

llvm-svn: 89723

llvm-svn: 89700

llvm-svn: 89478

llvm-svn: 87054

llvm-svn: 86706

llvm-svn: 86548

llvm-svn: 86494

llvm-svn: 85410

llvm-svn: 85362

llvm-svn: 85186

ld / st pairs, etc.

llvm-svn: 83197

Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.

llvm-svn: 83191

llvm-svn: 82788

llvm-svn: 82483

llvm-svn: 78604

Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.

llvm-svn: 78321

llvm-svn: 78101

llvm-svn: 78085

Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.

llvm-svn: 78081

llvm-svn: 76390

llvm-svn: 75254

llvm-svn: 73252

llvm-svn: 60901

llvm-svn: 60487

llvm-svn: 59344

llvm-svn: 59234

llvm-svn: 59107

llvm-svn: 59104

llvm-svn: 59102

llvm-svn: 59088