Add support for emitting non-temporal stores for DAGs marked
non-temporal.  Fix from r96241 for botched encoding of MOVNTDQ.

Add documentation for !nontemporal metadata.

Add a simpler movnt testcase.

llvm-svn: 96386

to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.

llvm-svn: 96384

llvm-svn: 96383

llvm-svn: 96382

They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.

This patch handles ARM mode. Thumb2 will follow.

llvm-svn: 96381

o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)

llvm-svn: 96380

llvm-svn: 96378

terminator's list of successors.

llvm-svn: 96377

llvm-svn: 96372

llvm-svn: 96370

branch in ARM v4 code, since it gets clobbered by the return address before
it is used.  Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.

llvm-svn: 96360

methods to try to have the type predicates be more logically positioned.

llvm-svn: 96349

and T->isPointerTy().  Convert most instances of the first form to the second form.
Requested by Chris.

llvm-svn: 96344

llvm-svn: 96343

llvm-svn: 96337

not the end of the field, fixing rdar://7651978

llvm-svn: 96330

Currently, whether a function is ISR or not is encoded in the section attribute for that function.

llvm-svn: 96322

elimination.  Before a DBG_VALUE could affect codegen.
The solution here is imperfect and not final.

llvm-svn: 96318

llvm-gcc but has been replaced with pad argument which don't need any
special backend support.

llvm-svn: 96312

as it also peeks at which registers are being used by other uses. This
makes LSR less sensitive to use-list order.

llvm-svn: 96308

at older buildbot messages, I see the failure predates
this patch.

llvm-svn: 96307

finished.

llvm-svn: 96304

but it's harder to believe it's the other candidate,
so reverting.  Temporarily I hope.

llvm-svn: 96303

strict about the requirements.

llvm-svn: 96301

We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.

llvm-svn: 96297

llvm-svn: 96295

llvm-svn: 96294

llvm-svn: 96292

llvm-svn: 96290

llvm-svn: 96289

llvm-svn: 96288

It turns out that we emitted completely wrong common EH frame since the early beginning! The "z" CIE augmentation mark indicates that there is an extra word containing the size of augmentation section. However, even for frames w/o any augmentation data we emitted size uleb! (this is the case of "unwinding through C code"). Thus frame moves information was emitterd completely wrong.

llvm-svn: 96287

llvm-svn: 96286

Preliminary patch to improve dwarf EH generation - Hooks to return Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there

llvm-svn: 96285

'i1' type.

llvm-svn: 96282

A virtual register can be used before it is defined in the same MBB if the MBB
is part of a loop. Teach the implicit-def pass about this case.

llvm-svn: 96279

Module (we were called with verifyFunction and an unowned Function) we can't
rely on Mod->getContext().

llvm-svn: 96275

fixes a crash using FPM on a Function that isn't owned by a Module.

llvm-svn: 96273

functions not embedded within modules.

llvm-svn: 96272

llvm-svn: 96269