the ConvertToMCInst() return void, rather then a bool.  Update all the cvt
functions as well.

llvm-svn: 162961

llvm-svn: 162946

llvm-svn: 162945

an 80-column violation in the generated code.  No functional change intended.

llvm-svn: 162944

AsmMatcherEmitter.  This function maps inline assembly operands to MCInst
operands.

For example, '__asm mov j, eax' is represented by the follow MCInst:

<MCInst 1460 <MCOperand Reg:0> <MCOperand Imm:1> <MCOperand Reg:0> 
             <MCOperand Expr:(j)> <MCOperand Reg:0> <MCOperand Reg:43>>

The first 5 MCInst operands are a result of j matching as a memory operand
consisting of a BaseReg (Reg:0), MemScale (Imm:1), MemIndexReg(Reg:0), 
Expr (Expr:(j), and a MemSegReg (Reg:0).  The 6th MCInst operand represents
the eax register (Reg:43).

This translation is necessary to determine the Input and Output Exprs.  If a
single asm operand maps to multiple MCInst operands, the index of the first
MCInst operand is returned.  Ideally, it would return the operand we really
care out (i.e., the Expr:(j) in this case), but I haven't found an easy way
of doing this yet.

llvm-svn: 162920

Adding arbitrary records to ARM.td would break
basic-arm-instructions.s because selection of nop vs mov r0,r0 was
ambiguous (this will be tested by a subsequent addition to ARM.td).
An imperfect but sensible fix is to give precedence to match rules
that have more constraints.

llvm-svn: 162824

Both single-instruction and multi-instruction patterns can be checked
for missing mayLoad / mayStore, and hasSideEffects flags.

llvm-svn: 162734

Reviewed offline by chandlerc.

llvm-svn: 162623

Previously, instructions without a primary patterns wouldn't get their
properties inferred. Now, we use all single-instruction patterns for
inference, including 'def : Pat<>' instances.

This causes a lot of instruction flags to change.

- Many instructions no longer have the UnmodeledSideEffects flag because
  their flags are now inferred from a pattern.

- Instructions with intrinsics will get a mayStore flag if they already
  have UnmodeledSideEffects and a mayLoad flag if they already have
  mayStore. This is because intrinsics properties are linear.

- Instructions with atomic_load patterns get a mayStore flag because
  atomic loads can't be reordered. The correct workaround is to create
  pseudo-instructions instead of using normal loads. PR13693.

llvm-svn: 162614

Instructions are now only marked as variadic if they use variable_ops in
their ins list.

A variadic SDNode is typically used for call nodes that have the call
arguments as operands.

A variadic MachineInstr can actually encode a variable number of
operands, for example ARM's stm/ldm instructions. A call instruction
does not have to be variadic. The call argument registers are added as
implicit operands.

This change remove the MCID::Variadic flags from most call and return
instructions, allowing us to better verify their operands.

llvm-svn: 162599

It is now allowed to explicitly set hasSideEffects, mayStore, and
mayLoad on instructions with patterns.

Verify that the patterns are consistent with the explicit flags.

llvm-svn: 162569

Emit TableGen errors if guessInstructionProperties is 0 and
instruction properties can't be inferred from patterns.

Allow explicit instruction properties even when they can be inferred.

This patch doesn't change the TableGen output. Redundant properties
are not yet verified because the tree has errors.

llvm-svn: 162516

Keep track of the set/unset state of these bits along with their
true/false values, but treat '?' as '0' for now.

llvm-svn: 162461

Currently, TableGen just guesses instruction properties when it can't
infer them form patterns.

This adds a guessInstructionProperties flag to the instruction set
definition that will be used to disable guessing. The flag is intended
as a migration aid. It will be removed again when no more targets need
their properties guessed.

llvm-svn: 162460

llvm-svn: 162446

When reporting an error for a defm, we would previously only report the
location of the outer defm, which is not always where the error is.

Now we also print the location of the expanded multiclass defs:

lib/Target/X86/X86InstrSSE.td:2902:12: error: foo
  defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
             ^
lib/Target/X86/X86InstrSSE.td:2801:11: note: instantiated from multiclass
  defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
            ^
lib/Target/X86/X86InstrSSE.td:194:5: note: instantiated from multiclass
    def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
        ^

llvm-svn: 162409

No change in interface or functionality. Purely under-the-hood
details of the generated function that change.

The X86 assembly parser is reduced in size by over 15% and ARM by
over 10%.

No performance change by my measurements.

llvm-svn: 162337

llvm-svn: 162292

Patch by Vladimir Medic.

llvm-svn: 162124

llvm-svn: 162085

llvm-svn: 162082

Select instructions pick one of two virtual registers based on a
condition, like x86 cmov. On targets like ARM that support predication,
selects can sometimes be eliminated by predicating the instruction
defining one of the operands.

Teach PeepholeOptimizer to recognize select instructions, and ask the
target to optimize them.

llvm-svn: 162059

This can be used to tell TableGen to use a specific SubRegIndex instead
of synthesizing one when discovering all sub-registers.

llvm-svn: 161982

TableGen sometimes synthesizes missing sub-register indexes. Emit these
indexes as enumerators in the target namespace along with the
user-defined ones.

Also take this opportunity to stop creating new Record objects for
synthetic indexes.

llvm-svn: 161964

llvm-svn: 161940

Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.

As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:

Time to compile at -O2 (averaged w/ hot caches):
  Previous: 35.5s
  New:       8.9s

TEXT size:
  Previous: 447,251
  New:      297,661

Builds in 25% of the time previously required and generates code 66% of
the size.

Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.

llvm-svn: 161888

llvm-svn: 161657

This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.

llvm-svn: 161471

llvm-svn: 161298

Add more indirection to the disassembler tables to reduce amount of space used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data.

llvm-svn: 161101

llvm-svn: 161034

Tidy up. Move for loop index declarations into for statements. Use unsigned instead of uint16_t for loop indices. Use unsigned instead of uint32_t for arguments to raw_ostream.indent.

llvm-svn: 161033

llvm-svn: 161032

llvm-svn: 161031

llvm-svn: 161030

Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code.

llvm-svn: 160951

llvm-svn: 160950

Remove check for sub class of X86Inst from filter function since caller guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already.

llvm-svn: 160949

llvm-svn: 160948

Remove check for f256mem from has256BitOperands as nothing depended on it and it isn't the only 256-bit memory type anyway.

llvm-svn: 160946