llvm-svn: 163243

llvm-svn: 163242

llvm-svn: 163241

Avoid interleaving fprintf(stderr,...) and outs() << ...;

Also add a column to show "bytes-per" for each record.

llvm-svn: 163240

llvm-svn: 163235

Since TOC is just defined for PPC64, move its definition to PPC64 td file.

Patch by Adhemerval Zanella.

llvm-svn: 163234

llvm-svn: 163233

inteldialect.

llvm-svn: 163231

Previous patch accidentally decided it couldn't convert a VFP to a
NEON instruction after it had already destroyed the old one. Not a
good move.

llvm-svn: 163230

llvm-svn: 163229

llvm-svn: 163228

llvm-svn: 163225

Make sure to return a pointer into the target memory, not the local memory.
Often they are the same, but we can't assume that.

llvm-svn: 163217

Simulate a remote target address space by allocating a seperate chunk of
memory for the target and re-mapping section addresses to that prior to
execution. Later we'll want to have a truly remote process, but for now
this gets us closer to being able to test the remote target
functionality outside LLDB.

rdar://12157052

llvm-svn: 163216

It relies on clear() being fast and the cache rarely has more than 1 or 2
elements, so give it an inline capacity and always shrink it back down in case
it grows. DenseMap will grow to 64 buckets which makes clear() a lot slower.

llvm-svn: 163215

subreg_hireg of register pair Rp.

	* lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New
	 DenseMap similar to PeepholeMap that additionally records subreg info
	 too.
        (runOnMachineFunction): Record information in PeepholeDoubleRegsMap
        and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to
	the instruction Rx = COPY Rp1:logreg_subreg.
	* test/CodeGen/Hexagon/remove_lsr.ll: New test.
	

llvm-svn: 163214

llvm-svn: 163205

Fixed the DAG combiner to better handle the folding of AND nodes for vector types. The previous code was making the assumption that the length of the bitmask returned by isConstantSplat was equal to the size of the vector type. Now we first make sure that the splat value has at least the length of the vector lane type, then we only use as many fields as we have available in the splat value.

llvm-svn: 163203

llvm-svn: 163199

Remove some of the patterns added in r163196. Increasing the complexity on insert_subvector into undef accomplishes the same thing.

llvm-svn: 163198

Add patterns for integer forms of VINSERTF128/VINSERTI128 folded with loads. Also add patterns to turn subvector inserts with loads to index 0 of an undef into VMOVAPS.

llvm-svn: 163196

llvm-svn: 163195

llvm-svn: 163194

llvm-svn: 163193

Convert vextracti128/vextractf128 intrinsics to extract_subvector at DAG build time. Similar was previously done for vinserti128/vinsertf128. Add patterns for folding these extract_subvectors with stores.

llvm-svn: 163192

llvm-svn: 163191

llvm-svn: 163190

llvm-svn: 163187

llvm-svn: 163186

Reader/Writer.

llvm-svn: 163185

llvm-svn: 163184

llvm-svn: 163181

pointers-to-strong-pointers may be in play. These can lead to retains and
releases happening in unstructured ways, foiling the optimizer. This fixes
rdar://12150909.

llvm-svn: 163180

llvm-svn: 163179

Implicit uses can be dynamically tied to defs. This will soon be used
for predicated instructions on ARM.

llvm-svn: 163177

class.

llvm-svn: 163175

implementation does not co-exist well with how the sideeffect and alignstack
attributes are handled.  The reverts r161641.

llvm-svn: 163174

This doesn't seem ideal, perhaps we could just keep the llvm_site_cfg and have
other config (clang and clang-tools-extra) derive their site_cfg from that.

Suggestions/complaints/ideas welcome.

llvm-svn: 163171

Doesn't set MadeChange to TRUE if BypassSlowDivision doesn't change anything.

llvm-svn: 163165

Also a few minor changes:
- use pre-inc instead of post-inc
- use isa instead of dyn_cast
- 80 col
- trailing spaces

llvm-svn: 163164