- Jan 12, 2012
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Jakob Stoklund Olesen authored
llvm-svn: 148031
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Benjamin Kramer authored
Restore the (obviously wrong) behavior from before r147938 without relying on undefined behavior. Add a fat FIXME note. This should fix nightly tester failures. llvm-svn: 148030
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Nadav Rotem authored
Fix a bug in the AVX 256-bit shuffle code in cases where the splat element is on the boundary of two 128-bit vectors. The attached testcase was stuck in an endless loop. llvm-svn: 148027
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Benjamin Kramer authored
X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63. llvm-svn: 148024
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Devang Patel authored
In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
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Bill Wendling authored
need to make a deep copy of each of the std::maps. Use a std::map of the std::map instead. This improves the compile time of sqlite3 by ~2%. llvm-svn: 148003
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Devang Patel authored
This is a work in progress. llvm-svn: 148002
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Chandler Carruth authored
same pattern. We already had this pattern is a few places, but others tried to make a rough approximation of an actual DAG structure. As not everywhere went to this trouble, nothing could rely on this being done. In fact, I've checked all references to these node Ids, and the ones that are using the topo-sort properties are actually satisfied with a strict-weak-ordering. The requirement appears to be that Use >= Def. I've added a big blurb of comments to this bit of the transform to clarify why the order is so important for the next reader of the code. I'm starting with this change as it is very small, and trivially reverted if something breaks or the >= above really does need to be >. If that proves the case, we can hide the problem by reverting this patch, but the problem exists elsewhere as well, and so a more comprehensive solution will be needed. llvm-svn: 148001
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Bill Wendling authored
llvm-svn: 147980
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Jakob Stoklund Olesen authored
llvm-svn: 147979
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- Jan 11, 2012
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Bill Wendling authored
This appears to improve sqlite3's compile time by ~2%. llvm-svn: 147978
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Jakob Stoklund Olesen authored
This helper method is too simplistic for RAGreedy. llvm-svn: 147976
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Jakob Stoklund Olesen authored
llvm-svn: 147975
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Jakob Stoklund Olesen authored
No functional change. llvm-svn: 147972
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Eli Friedman authored
Re-fix the issue Bill fixed in r147899 in a slightly different way, which doesn't abuse the semantics of linker_private. We don't really want to merge any string constant with a weak_odr global. llvm-svn: 147971
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Eric Christopher authored
llvm-svn: 147966
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Argyrios Kyrtzidis authored
llvm-svn: 147965
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Nadav Rotem authored
When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. llvm-svn: 147964
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Rafael Espindola authored
This uses TLS slot 90, which actually belongs to JavaScriptCore. We only support frames with static size Patch by Brian Anderson. llvm-svn: 147960
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Rafael Espindola authored
Patch by Brian Anderson. llvm-svn: 147958
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Chandler Carruth authored
hoped this would revive one of the llvm-gcc selfhost build bots, but it didn't so it doesn't appear that my transform is the culprit. If anyone else is seeing failures, please let me know! llvm-svn: 147957
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Rafael Espindola authored
This is a comparison of two addresses, and GCC does the comparison unsigned. Patch by Brian Anderson. llvm-svn: 147954
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http://llvm.org/bugs/show_bug.cgi?id=11395Kostya Serebryany authored
[asan] extend the workaround for http://llvm.org/bugs/show_bug.cgi?id=11395: don't instrument the function at all on x86_32 if it has a large asm blob llvm-svn: 147953
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Rafael Espindola authored
Patch by Brian Anderson. llvm-svn: 147952
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Kevin Enderby authored
directives was in the wrong place and getting triggered incorectly with a cpp .file directive. This change fixes that and adds a test case. llvm-svn: 147951
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Jan Sjödin authored
llvm-svn: 147949
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Nadav Rotem authored
Fix a bug in the lowering of BUILD_VECTOR for AVX. SCALAR_TO_VECTOR does not zero untouched elements. Use INSERT_VECTOR_ELT instead. llvm-svn: 147948
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Duncan Sands authored
are invalid). Fixes a crash on array1.C from the GCC testsuite when compiled with dragonegg. llvm-svn: 147946
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Chandler Carruth authored
strange build bot failures that look like a miscompile into an infloop. I'll investigate this tomorrow, but I'd both like to know whether my patch is the culprit, and get the bots back to green. llvm-svn: 147945
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Chandler Carruth authored
lots of lines of code. No functionality changed. llvm-svn: 147942
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Chandler Carruth authored
SRL-rooted code. llvm-svn: 147941
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Chandler Carruth authored
factor the differences that were hiding in one of them into its other caller, the SRL handling code. No change in behavior. llvm-svn: 147940
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Chandler Carruth authored
mask+shift pairs at the beginning of the ISD::AND case block, and then hoist the final pattern into a helper function, simplifying and reflowing it appropriately. This should have no observable behavior change, but several simplifications fell out of this such as directly computing the new mask constant, etc. llvm-svn: 147939
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Jakob Stoklund Olesen authored
I don't think the compact encoding code is right, but at least is has defined behavior now. llvm-svn: 147938
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Chandler Carruth authored
extracts and scaled addressing modes into its own helper function. No functionality changed here, just hoisting and layout fixes falling out of that hoisting. llvm-svn: 147937
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Chandler Carruth authored
detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. llvm-svn: 147936
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Stepan Dyatkovskiy authored
1. Size heuristics changed. Now we calculate number of unswitching branches only once per loop. 2. Some checks was moved from UnswitchIfProfitable to processCurrentLoop, since it is not changed during processCurrentLoop iteration. It allows decide to skip some loops at an early stage. Extended statistics: - Added total number of instructions analyzed. llvm-svn: 147935
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Andrew Trick authored
This interface is misleading and dangerous, but it is actually what we need for unrolling. llvm-svn: 147926
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Rafael Espindola authored
llvm-svn: 147924
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Rafael Espindola authored
llvm-svn: 147923
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