Make it always return APInts with the same bitwidth for the same ConstantRange bitwidth to simply clients

llvm-svn: 160294

llvm-svn: 160293

[asan] a bit more refactoring, addressed some of the style comments from chandlerc, partially implemented crash callback merging (under flag)

llvm-svn: 160290

llvm-svn: 160289

llvm-svn: 160288

<string.h>. // rdar://11847319

llvm-svn: 160287

MSVC's implementation of isalnum will assert on characters > 255, so we need to use an unsigned char to ensure the integer promotion happens properly.  This fixes an assert in debug builds with CodeGen\X86\utf8.ll

llvm-svn: 160286

Relax the complete-type checks that are happening under __invokable<Fp, Args...> to only check Fp, and not Args... .  This should be sufficient to give the desired high quality diagnostics under both bind and function.  And this allows a test reported by Rich E on cfe-dev to pass.  Tracked by <rdar://problem/11880602>.

llvm-svn: 160285

[asan] refactor instrumentation to allow merging the crash callbacks (not fully implemented yet, no functionality change except the BB order)

llvm-svn: 160284

llvm-svn: 160283

llvm-svn: 160282

Fixing an MSVC warning -- the compiler did not like the cast added to work around a g++ bug (it would claim to possibly emit incorrect code).

llvm-svn: 160281

llvm-svn: 160280

Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn function, instead of assert(0).

llvm-svn: 160279

llvm-svn: 160278

Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63

Here is a description of DSLL:

Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits

Description: GPR[rd] <- GPR[rt] << (sa+32)

The 64-bit doubleword contents of GPR rt are shifted left, inserting
 zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.

This patch implements the direct object output of these instructions.

llvm-svn: 160277

llvm-svn: 160276

Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> and <llvm/TypeBuilder.h>

llvm-svn: 160275

1. FileCheck-ize epilogue.ll and allow another asm instruction to restore %rsp.
2. Remove check in widen_arith-3.ll that was hitting instruction in epilogue instead of
vector add.

llvm-svn: 160274

llvm-svn: 160273

llvm-svn: 160272

llvm-svn: 160271

llvm-svn: 160270

llvm-svn: 160269

llvm-svn: 160268

llvm-svn: 160267

tsan: port Go runtime to Darwin

llvm-svn: 160266

The new clang-ast-dump tool for selective AST dumping. Moved common command-line tool stuff to CommandLineClangTool

llvm-svn: 160265

llvm-svn: 160264

llvm-svn: 160263

[Sanitizer] implement straightforward nlogn sorting, as qsort() may call malloc, which leads to deadlock in ASan allocator

llvm-svn: 160262

Cast instruction do not have side effects and can consequently be part of a
scop. We special cased them earlier, as they may be problematic within array
subscripts or loop bounds. However, the scalar evolution validator already
checks for them such that there is no need to also check the instructions within
the basic blocks.  Checking them is actually overly conservative as the precence
of casts may invalidate a scop, even though scalar evolution is not influenced
by it.

llvm-svn: 160261

undef virtual register. The problem is that ProcessImplicitDefs removes the
definition of the register and marks all uses as undef. If we lose the undef
marker then we get a register which has no def, is not marked as undef. The
live interval analysis does not collect information for these virtual
registers and we crash in later passes.

Together with Michael Kuperstein <michael.m.kuperstein@intel.com>

llvm-svn: 160260

llvm-svn: 160259

llvm-svn: 160258

llvm-svn: 160257

It turns out that ASan relied on the at-the-end block insertion order to
(purely by happenstance) disable some LLVM optimizations, which in turn
start firing when the ordering is made more "normal". These
optimizations in turn merge many of the instrumentation reporting calls
which breaks the return address based error reporting in ASan.

We're looking at several different options for fixing this.

llvm-svn: 160256

llvm-svn: 160255

This is particularly useful to the backend code generators which try to
process things in the incoming function order.

Also, cleanup some uses of IRBuilder to be a bit simpler and more clear.

llvm-svn: 160254

functionality test.

In general, unless the functionality is substantially separated, we
should lump more basic testing into this file. The test running
infrastructure likes having a few test files with more comprehensive
testing within them.

llvm-svn: 160253