into the debug_ranges section.

llvm-svn: 191721

llvm-svn: 191720

llvm-svn: 191716

llvm-svn: 191715

llvm-svn: 191713

llvm-svn: 191712

on ADD16rr opcodes, if src1 != src, since that would cause 
convertToThreeAddress to try to create a virtual register. This is not
permitted after register allocation, which is when the X86FixupLEAs pass
runs.

This patch fixes PR16785.

llvm-svn: 191711

SEC_OFFSET from the beginning of the section so go ahead and emit
a label at the beginning of each one.

llvm-svn: 191710

toolchain.

Patch by Richard Pennington.

llvm-svn: 191706

Currently it will insert an illegal bitcast.
Arguably, the address space argument should be
added for the creation case.

llvm-svn: 191702

The test's output doesn't change, but this ensures
this is actually hit with a different address space.

llvm-svn: 191701

llvm-svn: 191699

No functionality change.

llvm-svn: 191696

This makes it consistent with other function pointers used in llvm-c

Differential Revision: http://llvm-reviews.chandlerc.com/D1712

llvm-svn: 191693

Changing the diagnostic message for out of range branch targets in 191686 broke the tests.

The diagnostic message for out of range branch targets was changed to be more consistent with the other diagnostics.
 

llvm-svn: 191691

llvm-svn: 191690

llvm-svn: 191689

This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.


Patch by Matheus Almeida

llvm-svn: 191688

This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.


Patch by Matheus Almeida

llvm-svn: 191687

Fix some LLVM Coding Standards violations.

No changes in functionality.

llvm-svn: 191686

This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.  


Patch by Matheus Almeida

llvm-svn: 191685

 and not an MSA register

Patch by Matheus Almeida

llvm-svn: 191684

llvm-svn: 191683

Patch by Richard Sandiford.

llvm-svn: 191680

This reverts commit r191670.

It was causing build failures on the msvc bots:

http://bb.pgr.jp/builders/ninja-clang-i686-msc17-R/builds/5166/steps/compile/logs/stdio

llvm-svn: 191679

[ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers.

See ARM ARM A8.8.72.

Violating this constraint results in unpredictable behavior.

llvm-svn: 191678

Those writes really need two/three uops.

llvm-svn: 191677

llvm-svn: 191676

llvm-svn: 191675

Defines away the issue where cast<Instruction> would fail because constant
folding happened. Also slightly cleaner.

llvm-svn: 191674

Inspired by the object from the SLPVectorizer. This found a minor bug in the
debug loc restoration in the vectorizer where the location of a following
instruction was attached instead of the location from the original instruction.

llvm-svn: 191673

They don't depend on the templated stuff.

llvm-svn: 191672

For targets that have instruction itineraries this means no change. Targets
that move over to the new schedule model will use be able the new schedule
module for instruction latencies in the if-converter (the logic is such that if
there is no itineary we will use the new sched model for the latencies).

Before, we queried "TTI->getInstructionLatency()" for the instruction latency
and the extra prediction cost. Now, we query the TargetSchedule abstraction for
the instruction latency and TargetInstrInfo for the extra predictation cost. The
TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if
an itinerary exists, otherwise it will use the new schedule model.

ATTENTION: Out of tree targets!

(I will also send out an email later to LLVMDev)

This means, if your target implements

 unsigned getInstrLatency(const InstrItineraryData *ItinData,
                          const MachineInstr *MI,
                          unsigned *PredCost);

and returns a value for "PredCost", you now also need to implement

 unsigned getPredictationCost(const MachineInstr *MI);

(if your target uses the IfConversion.cpp pass)

radar://15077010

llvm-svn: 191671

Enable building the LTO library (.lib and.dll) and llvm-lto.exe on Windows with
MSVC and Mingw as well as re-enabling the associated test.

Patch by Greg Bedwell!

llvm-svn: 191670

when it was actually a Constant*.

There are quite a few other casts to Instruction that might have the same problem,
but this is the only one I have a test case for.

llvm-svn: 191668

llvm-svn: 191664

For some reason, adding definitions for these load and store
instructions changed whether some of the build bots matched
comparisons as signed or unsigned.

llvm-svn: 191663

llvm-svn: 191661

The only thing this does on its own is make the definitions of RISB[HL]G
a bit more precise.  Those instructions are only used by the MC layer at
the moment, so no behavioral change is intended.  The class is needed by
later patches though.

llvm-svn: 191660

Use subreg_hNN and subreg_lNN for the high and low NN bits of a register.
List the low registers first, so that subreg_l32 also means the low 32
bits of a 128-bit register.

Floats are stored in the upper 32 bits of a 64-bit register, so they
should use subreg_h32 rather than subreg_l32.

No behavioral change intended.

llvm-svn: 191659