optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.

llvm-svn: 98683

handling constant unions.

llvm-svn: 98680

This is for the disassembly work.

There are cases where this is not possible, for example, A8.6.53 LDM Encoding T1.
In such case, we'll use an adhoc approach to deduce the Opcode programmatically.

llvm-svn: 98679

be doing something useful.

llvm-svn: 98677

llvm-svn: 98675

llvm-svn: 98673

str[r]chr returns its pointer argument so we cannot mark it as nocapture. Thanks to Duncan for spotting my mistake.

llvm-svn: 98671

llvm-svn: 98666

llvm-svn: 98663

llvm-svn: 98662

llvm-svn: 98656

llvm-svn: 98654

llvm-svn: 98653

general.

llvm-svn: 98649

llvm-svn: 98648

instructions for ld/st with writeback, the flag is completely redundant.

llvm-svn: 98643

llvm-svn: 98642

U    test/CodeGen/ARM/tls2.ll
U    test/CodeGen/ARM/arm-negative-stride.ll
U    test/CodeGen/ARM/2009-10-30.ll
U    test/CodeGen/ARM/globals.ll
U    test/CodeGen/ARM/str_pre-2.ll
U    test/CodeGen/ARM/ldrd.ll
U    test/CodeGen/ARM/2009-10-27-double-align.ll
U    test/CodeGen/Thumb2/thumb2-strb.ll
U    test/CodeGen/Thumb2/ldr-str-imm12.ll
U    test/CodeGen/Thumb2/thumb2-strh.ll
U    test/CodeGen/Thumb2/thumb2-ldr.ll
U    test/CodeGen/Thumb2/thumb2-str_pre.ll
U    test/CodeGen/Thumb2/thumb2-str.ll
U    test/CodeGen/Thumb2/thumb2-ldrh.ll
U    utils/TableGen/TableGen.cpp
U    utils/TableGen/DisassemblerEmitter.cpp
D    utils/TableGen/RISCDisassemblerEmitter.h
D    utils/TableGen/RISCDisassemblerEmitter.cpp
U    Makefile.rules
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/Makefile
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D    lib/Target/ARM/Disassembler
U    lib/Target/ARM/ARMInstrFormats.td
U    lib/Target/ARM/ARMAddressingModes.h
U    lib/Target/ARM/Thumb2ITBlockPass.cpp

llvm-svn: 98640

(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, #28]

llvm-svn: 98637

This does not move entirely to UAL syntax, since the default "increment after"
suffix is empty but we still use "IA" for that.

llvm-svn: 98635

llvm-svn: 98634

llvm-svn: 98633

llvm-svn: 98632

llvm-svn: 98628

llvm-svn: 98627

llvm-svn: 98625

adjusted unittest

I have added some doxygen to OptionalOperandTraits,
so hopefully there will be no confusion in the future.

Incidentally OptionalOperandTraits is not used any more (IIUC),
but the obvious client would be BranchInstr, and I plan
to rearrange it that way.

llvm-svn: 98624

llvm-svn: 98623

works for me: bugpoint Output/bisort.llvm.bc -run-llc-ia -safe-run-llc

This uses llc with the integrated assembler as the test compiler and llc
without it as the safe compiler.

llvm-svn: 98618

llvm-svn: 98616

with the integrated assembler!

llvm-svn: 98615

llvm-svn: 98612

llvm-svn: 98610

llvm-svn: 98604

llvm-svn: 98602

"used outside of the block". If the block ends in a return, then it won't be
used outside of it.

llvm-svn: 98599

have enums for them.

llvm-svn: 98597

llvm-svn: 98596

to LLVM IR changes with addr label weirdness.  In the testcase, we
generate references to the two bb's when codegen'ing the first
function:

_test1:                                 ## @test1
	leaq	Ltmp0(%rip), %rax
..
	leaq	Ltmp1(%rip), %rax

Then continue to codegen the second function where the blocks
get merged.  We're now smart enough to emit both labels, producing
this code:

_test_fun:                              ## @test_fun
## BB#0:                                ## %entry
Ltmp1:                                  ## Block address taken
Ltmp0:
## BB#1:                                ## %ret
	movl	$-1, %eax
	ret

Rejoice.

llvm-svn: 98595

 - Although it would be nice to allow this decoupling, the assembler needs to be able to reason about MCSymbolRefExprs in too many places to make this viable. We can use a target specific encoding of the variant if this becomes an issue.
 - This patch also extends llvm-mc to support parsing of the modifiers, as opposed to lumping them in with the symbol.

llvm-svn: 98592