enabled by passing -tailcallopt to llc.  The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
  elf/pic enabled + callee is in module + callee has
  visibility protected or hidden

llvm-svn: 42870

llvm-svn: 42787

llvm-svn: 42786

llvm-svn: 42785

llvm-svn: 42783

llvm-svn: 42774

use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762

llvm-svn: 42761

llvm-svn: 42739

llvm-svn: 42738

llvm-svn: 42700

llvm-svn: 42699

(vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 
(vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
Remove x86 specific patterns.

llvm-svn: 42677

to its inverse.
Testing this as llcbeta

llvm-svn: 42661

llvm-svn: 42656

llvm-svn: 42655

cause performance degradation.

llvm-svn: 42653

leal 1(%ecx), %edi, which requires 67H prefix.

llvm-svn: 42647

llvm-svn: 42642

llvm-svn: 42640

llvm-svn: 42638

for consistency.

llvm-svn: 42637

llvm-svn: 42630

llvm-svn: 42624

llvm-svn: 42623

llvm-svn: 42607

of comparing begin() and end().

llvm-svn: 42585

llvm-svn: 42579

seem significant as well.

llvm-svn: 42564

llvm-svn: 42554

llvm-svn: 42552

llvm-svn: 42549

llvm-svn: 42548

llvm-svn: 42547

llvm-svn: 42546

llvm-svn: 42542

instructions reverse map.

llvm-svn: 42509

llvm-svn: 42492

And not super's super, either.

llvm-svn: 42482

llvm-svn: 42459