llvm-svn: 140465

Implement Duncan's suggestion to use the result of getSetCCResultType if it is legal
(this is always the case for scalars), otherwise use the promoted result type.

Fix test/CodeGen/X86/vsplit-and.ll when promote-elements is enabled.

llvm-svn: 140464

When generating the trunc-store of i1's, we need to use the vector type and not
the scalar type.

This patch fixes the assertion in CodeGen/Generic/bool-vector.ll when
running with -promote-elements.

llvm-svn: 140463

llvm-svn: 140446

llvm-svn: 140443

llvm-svn: 140441

llvm-svn: 140433

No test case. Noticed by inspection and I doubt it ever affects the
outcome of the overall heuristic, let alone final codegen.

llvm-svn: 140431

This exposes a -segmented-stacks bug.

llvm-svn: 140429

PR10998: It is not legal to sink an instruction past the terminator of a block; make sure we don't do that.

llvm-svn: 140428

llvm-svn: 140426

Math is hard, and isScaledConstantInRange() always returned false for
negative constants.  It was doing unsigned division of negative numbers
before casting back to signed.

llvm-svn: 140425

llvm-svn: 140422

Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.

llvm-svn: 140420

llvm-svn: 140415

llvm-svn: 140413

llvm-svn: 140412

llvm-svn: 140401

llvm-svn: 140397

callee-saved registers and reserved registers.

llvm-svn: 140395

llvm-svn: 140394

patch contributed by Jia Liu!

llvm-svn: 140391

llvm-svn: 140390

llvm-svn: 140387

llvm-svn: 140386

Original patch by Liu.

llvm-svn: 140385

hadd/hsub intrinsics into the new fhadd/fhsub X86 node.

llvm-svn: 140383

llvm-svn: 140378

llvm-svn: 140377

From 5936c03172e251f12a0332d1033de5718e6e2091 Mon Sep 17 00:00:00 2001
---
 lib/Target/PTX/PTXInstrInfo.td          |  165 ++++++++++++++++++++----------
 lib/Target/PTX/PTXIntrinsicInstrInfo.td |   88 +++++++++++------
 2 files changed, 167 insertions(+), 86 deletions(-)

llvm-svn: 140376

llvm-svn: 140375

llvm-svn: 140374

DecomposeMERGE_VALUES to "know" that results are legalized in
a particular order, by passing it the number of the result
being legalized (the type legalization core provides this, it
just needs to be passed on).

llvm-svn: 140373

integer-promotion of CONCAT_VECTORS.

Test: test/CodeGen/X86/widen_shuffle-1.ll

This patch fixes the above tests (when running in with -promote-elements).

llvm-svn: 140372

llvm-svn: 140366

Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.

llvm-svn: 140363

llvm-svn: 140356

PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage.  (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.)

llvm-svn: 140355

complain it cannot infer types in patterns. Fix a mistake in definition of 
SDT_MipsExtractElementF64.

llvm-svn: 140354

llvm-svn: 140352