RegisterCoalescer can create sub-register defs when it is joining a
register with a sub-register.  Add <undef> flags to these new
sub-register defs where appropriate.

llvm-svn: 141138

Teach the MC to output code/data region marker labels in MachO and ELF modes.  These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.

llvm-svn: 141135

using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 141129

llvm-svn: 141125

The <undef> flag says that a MachineOperand doesn't read its register,
or doesn't depend on the previous value of its register.

A full register def never depends on the previous register value.  A
partial register def may depend on the previous value if it is intended
to update part of a register.

For example:

  %vreg10:dsub_0<def,undef> = COPY %vreg1
  %vreg10:dsub_1<def> = COPY %vreg2

The first copy instruction defines the full %vreg10 register with the
bits not covered by dsub_0 defined as <undef>.  It is not considered a
read of %vreg10.

The second copy modifies part of %vreg10 while preserving the rest.  It
has an implicit read of %vreg10.

This patch adds a MachineOperand::readsReg() method to determine if an
operand reads its register.

Previously, this was modelled by adding a full-register <imp-def>
operand to the instruction.  This approach makes it possible to
determine directly from a MachineOperand if it reads its register.  No
scanning of MI operands is required.

llvm-svn: 141124

llvm-svn: 141123

llvm-svn: 141122

llvm-svn: 141118

llvm-svn: 141117

llvm-svn: 141116

llvm-svn: 141115

llvm-svn: 141114

llvm-svn: 141113

llvm-svn: 141111

llvm-svn: 141110

llvm-svn: 141108

llvm-svn: 141107

This should unbreak the Windows build.

llvm-svn: 141105

llvm-svn: 141104

llvm-svn: 141103

Add a test to do list manipulation and pass the result as arguments.
This tests the new list element operator resolve code and provides an
example of using list manipulation to do instruction pattern
substitution.

llvm-svn: 141102

When resolving an operator list element reference, resolve all
operator operands and try to fold the operator first.  This allows the
operator to collapse to a list which may then be indexed.

Before, it was not possible to do this:
class D<int a, int b> { ... }
class C<list<int> A> : D<A[0], A[1]>;
class B<list<int> b> : C<!foreach(...,b)>;

Now it is.

llvm-svn: 141101

llvm-svn: 141099

llvm-svn: 141097

llvm-svn: 141096

Put GCOVFile and other related interface in a common header so that llvm-cov tool can share it with GCOV writer.

llvm-svn: 141095

llvm-svn: 141093

llvm-svn: 141092

The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.

This patch implements the easiest form of register class inference:  For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.

This does create some new register classes for the targets in the tree:

ARM gets a new QQQQPR_with_ssub_0.  This class was omitted from the .td
file on purpose because it only has two registers.  InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.

PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8.  I think that might be an omission?

X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:

  GR64_with_sub_8bit
  GR64_TC_with_sub_8bit
  GR64_NOREX_with_sub_8bit
  GR64_TC_with_sub_8bit_hi

The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.

llvm-svn: 141084

This has already been done for most other targets.

llvm-svn: 141083

There is no need to keep the primary order separate.

llvm-svn: 141082

When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference.  All register classes must have a
name, though.

llvm-svn: 141081

The RecordKeeper could be shared by multiple target instances, causing
duplicate record errors.

llvm-svn: 141080

This patch adds a preprocessor that can expand nested for-loops for
saving some copy-n-paste in *.td files.

The preprocessor is not yet integrated with TGParser, and so it has
no direct effect on *.td inputs.  However, you may preprocess an td
input (and only preprocess it).

To test the proprecessor, type:
  tblgen -E -o $@ $<

llvm-svn: 141079

llvm-svn: 141075

Test: CellSPU/v2i32.ll when running with -promote-elements
llvm-svn: 141074

llvm-svn: 141066

Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.

llvm-svn: 141065

This handles the case in which LSR rewrites an IV user that is a phi and
splits critical edges originating from a switch.
Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely"

llvm-svn: 141059

llvm-svn: 141058