llvm-svn: 84813

llvm-svn: 84751

llvm-svn: 84144

llvm-svn: 84122

llvm-svn: 84117

vld lane intrinsics.

llvm-svn: 84110

llvm-svn: 84109

by creating TargetConstants during instruction selection instead of during
legalization.

llvm-svn: 84042

be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.

llvm-svn: 84022

llvm-svn: 84017

llvm-svn: 84009

llvm-svn: 83600

llvm-svn: 83598

llvm-svn: 83596

Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590

llvm-svn: 83585

llvm-svn: 83568

llvm-svn: 83566

llvm-svn: 83565

llvm-svn: 83526

llvm-svn: 83518

llvm-svn: 83513

llvm-svn: 83508

llvm-svn: 83506

llvm-svn: 83502

llvm-svn: 83486

llvm-svn: 83484

llvm-svn: 83482

llvm-svn: 83479

llvm-svn: 83471

This is just to be more consistent with the forthcoming code for vld3/4.

llvm-svn: 83470

llvm-svn: 83422

Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel.  Radar 7250345.

llvm-svn: 82988

This should be better than single load from constpool.

llvm-svn: 82948

naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.

llvm-svn: 82790

llvm-svn: 80707

llvm-svn: 80656

The instructions can be selected directly from the intrinsics.  We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.

llvm-svn: 80117

llvm-svn: 79742

llvm-svn: 79625