that Makefile.common would see it.

llvm-svn: 6367

Also, added annotations to how instructions are modified (reg/imm operands).
Added prototype for adding register numbers to values pass for interfacing with
the target-independent register allocators in the JIT.

llvm-svn: 6366

MachineCodeEmitter to make a pass-through debugger -- output to memory and to
std::cerr.

llvm-svn: 6363

of Sparc JIT (printing out instrs) on X86. Con: this increases linking time.

llvm-svn: 6361

`lli -march=x86' or `lli -march=sparc' will forcefully select the JIT even on a
different platform. Running lli without the -march option will select the JIT
for the platform that it's currently running on.

Pro: can test Sparc JIT (debug printing mode) on X86 -- faster to compile/link
LLVM source base to test changes.
Con: Linking lli on x86 now pulls in all the Sparc libs -> longer link time
(but X86 can bear it, right?)

In the future, perhaps this should be a ./configure option to enable/disable
target JITting...

llvm-svn: 6360

that assembles instructions is generated via TableGen (and hence must be built
before building this directory, but that's already the case in the top-level
Makefile).

Also added is .cvsignore to ignore the generated file `SparcV9CodeEmitter.inc',
which is included by SparcV9CodeEmitter.cpp .

llvm-svn: 6357

llvm-svn: 6356

llvm-svn: 6355

llvm-svn: 6352

llvm-svn: 6351

* Implement SRoA for arrays

llvm-svn: 6349

llvm-svn: 6346

and related functions and flags.  Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".

llvm-svn: 6342

    Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341

llvm-svn: 6340

Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.

llvm-svn: 6339

llvm-svn: 6338

negative values.  Need to add one to a negative value before right shift!

llvm-svn: 6334

llvm-svn: 6333

llvm-svn: 6332

llvm-svn: 6328

llvm-svn: 6325

llvm-svn: 6323

llvm-svn: 6320

This was a problem with constants having their types resolved to some new type,
but there was already a constant of the new type created.  Before, these types
were never merged together, now they are.

llvm-svn: 6314

llvm-svn: 6312

llvm-svn: 6306

llvm-svn: 6305

llvm-svn: 6304

llvm-svn: 6303

llvm-svn: 6302

llvm-svn: 6301

llvm-svn: 6300

llvm-svn: 6295

llvm-svn: 6294

llvm-svn: 6291

  function and no symbols were explicitly marked to be externalized.
* Add new -internalize-public-api-list option that can be used if the symbol
  list is small, and making a new file is annoying.

llvm-svn: 6289

should not be internalized

llvm-svn: 6288

This hunk:
-    } else if (Src->getNumOperands() == 2 && Src->use_size() == 1) {
+    } else if (Src->getNumOperands() == 2) {

Allows GEP folding to be more aggressive, which reduces the number of instructions
and can dramatically speed up BasicAA in some cases.

llvm-svn: 6286

by emitting the type planes before any constants (which could be constant
expressions involving undefined types!)

llvm-svn: 6285