isInteger, we now have isFloatTy and isIntegerTy.  Requested by Chris!

llvm-svn: 96223

llvm-svn: 96174

Otherwise AT&T asm printer is used with non-compatible MCAsmInfo and
there is no way to override this behaviour.

llvm-svn: 96165

encoding them into nothing.

llvm-svn: 96110

llvm-svn: 96088

llvm-svn: 96076

tables.

llvm-svn: 96073

created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.

llvm-svn: 96069

llvm-svn: 96065

We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.

llvm-svn: 96059

fix swapgs to be spelled right.

llvm-svn: 96058

llvm-svn: 96055

encoder and decoder by using new MRM_ forms.

llvm-svn: 96048

rip-relative addresses, and add a testcase.

llvm-svn: 96040

llvm-svn: 96038

addressing.  This isn't complete because I need an MCContext
to generate new MCExprs.

llvm-svn: 96036

llvm-svn: 96031

llvm-svn: 96029

llvm-svn: 96028

is pc relative or not, mark call and branches as pcrel.

llvm-svn: 96026

llvm-svn: 96011

llvm-svn: 95981

This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936

llvm-svn: 95980

This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.

llvm-svn: 95960

great solution for the disassembler, we'll go with "plan b".

llvm-svn: 95957

with "tied memory operands", which is wrong.

llvm-svn: 95950

llvm-svn: 95949

movq	(%ecx,%edx,2), %xmm2
movhps	(%ecx,%eax,2), %xmm2

rather than:

movq     (%eax, %edx, 2), %xmm2		
movq     (%eax, %ebx, 2), %xmm3		
movlhps  %xmm3, %xmm2			

Testcase forthcoming.

llvm-svn: 95948

busted in both encoders.  I'm not bothering to fix it in the
old one at this point.

llvm-svn: 95947

	testb	%al, %al                ## <MCInst #2412 TEST8rr
                                        ##   <MCOperand Reg:2>
                                        ##   <MCOperand Reg:2>>
	jne	LBB1_7                  ## <MCInst #938 JNE_1
                                        ##   <MCOperand Expr:(LBB1_7)>>

llvm-svn: 95935

implemented, llvm-mc --show-inst now uses it to print the
instruction opcode as well as the number.

llvm-svn: 95929

8 or 32-bit immediates, which allows the new encoder to handle
them.

llvm-svn: 95927

the tables to be const.  Teach MCCodeEmitter to handle
the target-indep kinds so that we don't crash on them.

llvm-svn: 95924

llvm-svn: 95920

llvm-svn: 95915

use a multipattern that generates both the 1-byte and 4-byte 
versions from the same defm

llvm-svn: 95901

fixes the remaining x86-64 jit failures afaik.

llvm-svn: 95867

r12b, etc) also encodes to a R/M value of 4, which is just
as illegal as ESP/RSP for the non-sib version an address.

This fixes x86-64 jit miscompilations of a bunch of programs.

llvm-svn: 95866

Stub out some dummy fixups to make things work.

We can now emit fixups like this:
	subl	$20, %esp               ## encoding: [0x83,0xec,A]
                                        ##   fixup A - offset: 2, value: 20, kind: fixup_1byte_imm

Emitting $20 as a single-byte fixup to be later resolved
by the assembler is ridiculous of course (vs just emitting
the byte) but this is a failure of the matcher, which 
should be producing an imm of 20, not an MCExpr of 20.

llvm-svn: 95860

and rename it to EmitImmediate.

llvm-svn: 95859