llvm-svn: 41774

The x86-64 ABI states that objects passed on the stack have
8 byte alignment. Implement that.

llvm-svn: 41768

Patch by Sterling Stein!

llvm-svn: 41758

Use APFloat in UpgradeParser and AsmParser.
Change all references to ConstantFP to use the
APFloat interface rather than double.  Remove
the ConstantFP double interfaces.
Use APFloat functions for constant folding arithmetic
and comparisons.
(There are still way too many places APFloat is
just a wrapper around host float/double, but we're
getting there.)

llvm-svn: 41747

leal    (,%rcx,8), %rcx
It should be
leal    (,%rcx,8), %ecx

llvm-svn: 41735

llvm-svn: 41700

llvm-svn: 41680

llvm-svn: 41643

This is mandated table 3.1 at
http://www.x86-64.org/documentation/abi.pdf

llvm-svn: 41642

Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.

llvm-svn: 41632

Added support to fold X86 load / store instructions. This allow rematerialized loads to be folded into their uses.

llvm-svn: 41599

llvm-svn: 41595

Add APFloat interfaces to ConstantFP, SelectionDAG.
Fix integer bit in double->APFloat conversion.
Convert LegalizeDAG to use APFloat interface in
ConstantFPSDNode uses.

llvm-svn: 41587

in the trampoline lowering.  Lookup the jump and
mov opcodes for the trampoline rather than hard
coding them.

llvm-svn: 41577

llvm-svn: 41502

Coping 100MB array (after a warmup) shows that glibc 2.6.1 implementation on
x86-64 (core 2) is 30% faster (from 0.270917s to 0.188079s)

llvm-svn: 41479

changing the interface to allow for future changes.

llvm-svn: 41384

llvm-svn: 41359

llvm-svn: 41319

llvm-svn: 41284

llvm-svn: 41208

 *) The needed information is propagated to the DAG
 *) The X86-64 backend detects it and aborts

llvm-svn: 41179

llvm-svn: 41178

hard to catch bugs with retaddr lowering

llvm-svn: 41104

llvm-svn: 41103

llvm-svn: 41059

see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.

llvm-svn: 41049

llvm-svn: 41048

llvm-svn: 41021

able to 3-addressify away stuff like this:

        movl    %ecx, %eax
        decl    %eax

llvm-svn: 41020

Make a 'memop' pattern just for them.

llvm-svn: 41017

llvm-svn: 41013

Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)).

llvm-svn: 41010

llvm-svn: 41009

Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.

llvm-svn: 41007

llvm-svn: 40986

llvm-svn: 40985

llvm-svn: 40982

llvm-svn: 40973

divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead.

llvm-svn: 40972