llvm-svn: 78216

llvm-svn: 78212

llvm-svn: 78211

llvm-svn: 78209

llvm-svn: 78207

Patch by Neale Ferguson!

llvm-svn: 78203

llvm-svn: 78200

llvm-svn: 78191

llvm-svn: 78189

llvm-svn: 78182

llvm-svn: 78181

Patch by Sandeep Patel

llvm-svn: 78180

a dirty hack and isn't need anymore since the last x86 code emitter patch)
- Add a target-dependent modifier to addend calculation
- Use R_X86_64_32S relocation for X86::reloc_absolute_word_sext
- Use getELFSectionFlags whenever possible
- fix getTextSection to use TLOF and emit the right text section 
- Handle global emission for static ctors, dtors and Type::PointerTyID
- Some minor fixes

llvm-svn: 78176

llvm-svn: 78175

MMX arguments. This fixes PR4684.

llvm-svn: 78163

them in the verifier.

llvm-svn: 78160

getKindForGlobal.

llvm-svn: 78156

llvm-svn: 78146

Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.

llvm-svn: 78142

llvm-svn: 78138

calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.

llvm-svn: 78137

Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions.  The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.

llvm-svn: 78136

for ELF to work.  
2) RIP addressing: Use SIB bytes for absolute relocations where RegBase=0, 
IndexReg=0.
3) The JIT can get the real address of cstpools and jmptables during
code emission, fix that for object code emission

llvm-svn: 78129

llvm-svn: 78126

For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.

llvm-svn: 78109

llvm-svn: 78105

llvm-svn: 78104

still get "intel syntax" instructions from llc with  
-x86-asm-syntax=intel

llvm-svn: 78103

llvm-svn: 78101

the masm backend.  If anyone cares about masm in the future,
we'll have semantic sections it can hang off of.

llvm-svn: 78096

The only exception is CC.

llvm-svn: 78089

llvm-svn: 78086

llvm-svn: 78085

llvm-svn: 78082

Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.

llvm-svn: 78081

llvm-svn: 78070

__TEXT,__ustring section on darwin.

llvm-svn: 78068

it is just being used as a prefix, so forward substitute it directly.

llvm-svn: 78067

section on ELF targets.

llvm-svn: 78066

llvm-svn: 78060