[asan] asan_allocator2: by default use the StackDepot to store the stack traces instead of storing them in the redzones

llvm-svn: 171099

llvm-svn: 171098

llvm-svn: 171097

llvm-svn: 171096

llvm-svn: 171095

llvm-svn: 171094

llvm-svn: 171093

Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions.

llvm-svn: 171092

llvm-svn: 171091

llvm-svn: 171090

[asan] asan_allocator2: store the user requested size in just 32 bits (larger sizes use metadata). This allows to put one more 32-bit field into the chunk header

llvm-svn: 171089

Template instantiation can set the canonical decl to used after subsequent
decls have been chained, so we have to check that too.

llvm-svn: 171088

Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN

llvm-svn: 171087

llvm-svn: 171086

llvm-svn: 171085

llvm-svn: 171084

llvm-svn: 171083

llvm-svn: 171082

Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment...

llvm-svn: 171081

Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX.

llvm-svn: 171080

For the time being this includes only some dummy test cases. Once the
generic implementation of the intrinsics cost function does something other
than assuming scalarization in all cases, or some target specializes the
interface, some real test cases can be added.

Also, for consistency, I changed the type of IID from unsigned to Intrinsic::ID
in a few other places.

llvm-svn: 171079

Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment.

llvm-svn: 171078

This fixes pr14691, which I think is a regression from r168519.

llvm-svn: 171077

llvm-svn: 171076

llvm-svn: 171075

due to FORCE_CLANG_DIAGNOSTICS_CRASH=1. Also add a test for that env var.

llvm-svn: 171074

As with the prefetch intrinsic to which it maps, simply have dcbt
marked as reading from and writing to its arguments instead of having
unmodeled side effects. While this might cause unwanted code motion
(because aliasing checks don't really capture cache-line sharing),
it is more important that prefetches in unrolled loops don't block
the scheduler from rearranging the unrolled loop body.

llvm-svn: 171073

Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.

llvm-svn: 171072

llvm-svn: 171071

VectorType::getInteger() can not be used with them, because pointer size
depends on the target.

llvm-svn: 171070

llvm-svn: 171069

Changed getLocStart() and getLocEnd() to be required for Stmts, and make
getSourceRange() optional. The default implementation for getSourceRange()
is build the range by calling getLocStart() and getLocEnd().

llvm-svn: 171067

This only failed on hosts that don't have SSE41.

llvm-svn: 171066

llvm-svn: 171065

llvm-svn: 171064

pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack.
Small speedup on loop-vectorized viterbi (-march=core2).

llvm-svn: 171063

llvm-svn: 171062

llvm-svn: 171061

llvm-svn: 171060

llvm-svn: 171059