string of features for that target. However LTO was using that string to pass
into the "create target machine" stuff. That stuff needed the feature string to
be in a particular form. In particular, it needed the CPU specified first and
then the attributes. If there isn't a CPU specified, it required it to be blank
-- e.g., ",+altivec". Yuck.

Modify the getDefaultSubtargetFeatures method to be a non-static member
function. For all attributes for a specific subtarget, it will add them in like
normal. It will also take a CPU string so that it can satisfy this horrible
syntax.

llvm-svn: 103451

llvm-svn: 103437

llvm-svn: 103411

llvm-svn: 103399

changed dllexport code to use EmitBytes instead of EmitRawText, and changed the export option to use /EXPORT: instead of -export: on the windows platform

llvm-svn: 103377

llvm-svn: 103373

patch by Nathan Jeffords!

llvm-svn: 103346

whether the extract instructions are available.

rdar://7956878

llvm-svn: 103277

llvm-svn: 103276

llvm-svn: 103271

patch by Peter Housel!

llvm-svn: 103267

Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.

llvm-svn: 103235

Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.

llvm-svn: 103234

instruction, rather than a location near where the new instruction
is being inserted.

llvm-svn: 103232

Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.

llvm-svn: 103218

 - This fixes "leal 0, %eax", for example.

llvm-svn: 103205

llvm-svn: 103199

and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196

we don't currently support relaxing them.

llvm-svn: 103195

doesn't have to guess.

llvm-svn: 103194

llvm-svn: 103193

(replacing the previous patch for the same issue).

llvm-svn: 103183

llvm-svn: 103181

llvm-svn: 103179

Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.

llvm-svn: 103172

llvm-svn: 103163

   Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td

llvm-svn: 103159

llvm-svn: 103157

Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.

llvm-svn: 103156

llvm-svn: 103155

llvm-svn: 103154

instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136

that was causing PC-relative branch targets to be
evaluated incorrectly.  Also added support for
checking operand values to the llvm-mc tester.

llvm-svn: 103128

Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.

llvm-svn: 103124

user's source, so don't arbitrarily assign them a debug location.

llvm-svn: 103121

Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119

llvm-svn: 103104

llvm-svn: 103103

hack the code to turn it off when debugging.

llvm-svn: 103083

llvm-svn: 103057