llvm-svn: 57715

have an unreachable block in a function. This was triggering the assert. This is
a horrid hack to cover this up.

Oh! for a good debug info architecture!

llvm-svn: 57714

touches memory and need an associated MemOperand

llvm-svn: 57712

ISD condition opcodes into helper functions.

llvm-svn: 57710

that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand.

llvm-svn: 57699

llvm-svn: 57690

constraint.  Reject asms where an output has multiple
input constraints tied to it.

llvm-svn: 57687

array.  Improve some minor comments, refactor some helpers in
AsmOperandInfo.  No functionality change for valid code.

llvm-svn: 57686

llvm-svn: 57673

shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.

Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.

Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.

These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.

llvm-svn: 57662

llvm-svn: 57618

because it declares a std::vector<MachineMove>, and strict
concept checking requires the definition of MachineMove to be
available.

llvm-svn: 57617

computation. A def of a register doesn't necessarily kill
live super-registers.

llvm-svn: 57614

with other debug messages.

llvm-svn: 57543

i.e. conditions that cannot be checked with a single instruction. For example,
SETONE and SETUEQ on x86.
- Teach legalizer to implement *illegal* setcc as a and / or of a number of
legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is
implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ.
- Move x86 target over.

llvm-svn: 57542

 - Move the EH landing-pad code and adjust it so that it works
   with FastISel as well as with SDISel.
 - Add FastISel support for @llvm.eh.exception and
   @llvm.eh.selector.

llvm-svn: 57539

llvm-svn: 57526

instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.

llvm-svn: 57521

FIX PR2794. Make sure SIGN_EXTEND_INREG nodes introduced by LegalizeSetCCOperands are leglized. Patch by Richard Pennington.

llvm-svn: 57460

Also update sub-register intervals after a trivial computation is rematt'ed for a copy instruction. PR2775.

llvm-svn: 57458

   null. This assumes that any target that does not have AsmInfo, does not
   support "LocAndDot".

llvm-svn: 57438

NULL, but just hide some debug output then.

llvm-svn: 57437

llvm-svn: 57428

llvm-svn: 57424

llvm-svn: 57388

parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.

llvm-svn: 57385

llvm-svn: 57371

valid comments in inline assembly.
gcc.target/i386/20011009-1.c

llvm-svn: 57365

llvm-svn: 57339

and APFloat::convertToInteger.  Restore return value to
IEEE754.  Adjust all users accordingly.

llvm-svn: 57329

make it clearer what the function does.  No functional
change.

llvm-svn: 57325

thus aligning the label.

llvm-svn: 57310

Fix the case where an instruction is not properly marked as using all registers that alias its inputs.

llvm-svn: 57286

instead.

So now: -fast-isel or -fast-isel=true enable fast-isel, and
-fast-isel=false disables it. Fast-isel is also on by default
with -fast, and off by default otherwise.

llvm-svn: 57270

for things like null pointers, which at this level aren't
different from regular integer constants.

llvm-svn: 57265

llvm-svn: 57259

llvm-svn: 57255

llvm-svn: 57249

llvm-svn: 57248

llvm-svn: 57247