- Feb 24, 2004
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Alkis Evlogimenos authored
register mapping or a stack slot mapping. llvm-svn: 11795
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Alkis Evlogimenos authored
llvm-svn: 11782
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Alkis Evlogimenos authored
llvm-svn: 11781
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Alkis Evlogimenos authored
251 (providing a generic machine code rewriter/spiller). llvm-svn: 11780
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- Feb 23, 2004
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Alkis Evlogimenos authored
llvm-svn: 11759
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Chris Lattner authored
llvm-svn: 11758
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Chris Lattner authored
llvm-svn: 11757
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Alkis Evlogimenos authored
llvm-svn: 11756
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Alkis Evlogimenos authored
llvm-svn: 11755
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Alkis Evlogimenos authored
block into MachineBasicBlock::getFirstTerminator(). This also fixes a bug in the implementation of the above in both RegAllocLocal and InstrSched, where instructions where added after the terminator if the basic block's only instruction was a terminator (it shouldn't matter for RegAllocLocal since this case never occurs in practice). llvm-svn: 11748
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Alkis Evlogimenos authored
Improved PhysRegTracker interface. RegAlloc lazily allocates the register tracker using a std::auto_ptr llvm-svn: 11738
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Alkis Evlogimenos authored
Simplify iterator usage now that we have next(). Also don't pass iterators by reference now that MachineInstr* are in an ilist llvm-svn: 11732
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Alkis Evlogimenos authored
llvm-svn: 11724
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Alkis Evlogimenos authored
Fix comments in PhysRegTracker and rename isPhysRegAvail to isRegAvail to be consistent with the other two llvm-svn: 11723
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Alkis Evlogimenos authored
llvm-svn: 11721
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Alkis Evlogimenos authored
llvm-svn: 11720
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Alkis Evlogimenos authored
llvm-svn: 11719
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- Feb 22, 2004
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Chris Lattner authored
llvm-svn: 11716
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Chris Lattner authored
one terminator instruction in each basic block. llvm-svn: 11714
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Alkis Evlogimenos authored
llvm-svn: 11704
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Alkis Evlogimenos authored
Also make it less aggressive as the current implementation breaks in some cases. llvm-svn: 11696
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- Feb 21, 2004
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Alkis Evlogimenos authored
llvm-svn: 11687
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- Feb 20, 2004
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Alkis Evlogimenos authored
llvm-svn: 11676
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Alkis Evlogimenos authored
llvm-svn: 11675
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Alkis Evlogimenos authored
llvm-svn: 11674
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Alkis Evlogimenos authored
llvm-svn: 11659
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Alkis Evlogimenos authored
llvm-svn: 11655
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Alkis Evlogimenos authored
1. LiveIntervals now implement a 4 slot per instruction model. Load, Use, Def and a Store slot. This is required in order to correctly represent caller saved register clobbering on function calls, register reuse in the same instruction (def resues last use) and also spill code added later by the allocator. The previous representation (2 slots per instruction) was insufficient and as a result was causing subtle bugs. 2. Fixes in spill code generation. This was the major cause of failures in the test suite. 3. Linear scan now has core support for folding memory operands. This is untested and not enabled (the live interval update function does not attempt to fold loads/stores in instructions). 4. Lots of improvements in the debugging output of both live intervals and linear scan. Give it a try... it is beautiful :-) In summary the above fixes all the issues with the recent reserved register elimination changes and get the allocator very close to the next big step: folding memory operands. llvm-svn: 11654
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- Feb 19, 2004
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Alkis Evlogimenos authored
llvm-svn: 11629
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Chris Lattner authored
variable information to take into account the change of instruction address. llvm-svn: 11628
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Chris Lattner authored
llvm-svn: 11627
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Chris Lattner authored
llvm-svn: 11625
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Chris Lattner authored
by operator<< on MachineInstr's, and looking up what register "24" is all of the time was greatly annoying. llvm-svn: 11623
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Chris Lattner authored
llvm-svn: 11622
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Alkis Evlogimenos authored
llvm-svn: 11619
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Alkis Evlogimenos authored
llvm-svn: 11609
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- Feb 18, 2004
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Chris Lattner authored
llvm-svn: 11578
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Chris Lattner authored
llvm-svn: 11577
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Alkis Evlogimenos authored
llvm-svn: 11575
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Alkis Evlogimenos authored
llvm-svn: 11574
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