(except the part about choosing direction)

llvm-svn: 157437

llvm-svn: 157433

Like this:

  foreach i = 0-127 in ...

Use braces for composite ranges:

  foreach i = {0-3,9-7} in ...

llvm-svn: 157432

Only fully expanded Records should go into RecordKeeper.

llvm-svn: 157431

Use static type checking.

llvm-svn: 157430

llvm-svn: 157429

llvm-svn: 157428

The Hazard checker implements in-order contraints, or interlocked
resources. Ready instructions with hazards do not enter the available
queue and are not visible to other heuristics.

The major code change is the addition of SchedBoundary to encapsulate
the state at the top or bottom of the schedule, including both a
pending and available queue.

The scheduler now counts cycles in sync with the hazard checker. These
are minimum cycle counts based on known hazards.

Targets with no itinerary (x86_64) currently remain at cycle 0. To fix
this, we need to provide some maximum issue width for all targets. We
also need to add the concept of expected latency vs. minimum latency.

llvm-svn: 157427

llvm-svn: 157426

llvm-svn: 157425

llvm-svn: 157424

llvm-svn: 157423

llvm-svn: 157422

This back-end was deprecated in favor of the NVPTX back-end.

NV_CONTRIB

llvm-svn: 157417

Expand test case for this.

Patch by Reed Kotler.

llvm-svn: 157410

First code from the Mips16 compiler. Includes trivial test program.

Patch by Reed Kotler.

llvm-svn: 157408

I'm not sure it's really worth expressing this as a range rather than 3 specific equalities, but it doesn't seem fundamentally wrong either.

llvm-svn: 157398

Submitted by: Anton Lokhmotov  <Anton.Lokhmotov@arm.com>

Approved by: o Anton Korobeynikov
             o Micah Villmow
             o David Neto

llvm-svn: 157393

LowerSwitch::Clusterify : main functinality was replaced with CRSBuilder::optimize, so big part of Clusterify's code was reduced.
test/Transform/LowerSwitch/feature.ll - this test was refactored: grep + count was replaced with FileCheck usage.

llvm-svn: 157384

llvm-svn: 157381

llvm-svn: 157380

llvm-svn: 157377

llvm-svn: 157375

llvm-svn: 157374

Make some opcode tables static and const. Allows code to avoid making copies to pass the tables around.

llvm-svn: 157373

llvm-svn: 157369

llvm-svn: 157368

Mark a static table as const. Shrink opcode size in static tables to uint16_t. Simplify loop iterating over one of those tables. No functional change intended.

llvm-svn: 157367

llvm-svn: 157358

Live ranges with a constrained register class may benefit from splitting
around individual uses. It allows the remaining live range to use a
larger register class where it may allocate. This is like spilling to a
different register class.

This is only attempted on constrained register classes.

<rdar://problem/11438902>

llvm-svn: 157354

llvm-svn: 157349

llvm-svn: 157348

Now that the coalescer keeps live intervals and machine code in sync at
all times, it needs to deal with identity copies differently.

When merging two virtual registers, all identity copies are removed
right away. This means that other identity copies must come from
somewhere else, and they are going to have a value number.

Deal with such copies by merging the value numbers before erasing the
copy instruction. Otherwise, we leave dangling value numbers in the live
interval.

This fixes PR12927.

llvm-svn: 157340

Patch by Jush Lu <jush.msn@gmail.com>.

llvm-svn: 157336

llvm-svn: 157329

Apparently LLVM only stopped emitting this after LLVM 3.0

llvm-svn: 157325

inline threshold if the global inline threshold is lower (as for -Oz).

Reviewed by Chandler Carruth and Bill Wendling.

llvm-svn: 157323

llvm-svn: 157320

llvm-svn: 157319

llvm-svn: 157317