llvm-svn: 127619

llvm-svn: 127592

llvm-svn: 127575

llvm-svn: 127517

llvm-svn: 127510

llvm-svn: 127509

llvm-svn: 127508

llvm-svn: 127506

llvm-svn: 127491

as for VDUP32d and VDUP32q, respectively.

llvm-svn: 127489

llvm-svn: 127488

and VDUPLN32d, respectively.

llvm-svn: 127486

as for VREV64d32 and VREV64q32, respectively.

llvm-svn: 127485

the diagnostic.

llvm-svn: 127480

CodeGenRegister entries. Use this information to more intelligently build
the literal register entires in the DAGISel matcher table. Specifically,
use a single-byte OPC_EmitRegister entry for registers with a value of
less than 256 and OPC_EmitRegister2 entry for registers with a larger value.

rdar://9066491

llvm-svn: 127456

llvm-svn: 127448

llvm-svn: 127447

llvm-svn: 127446

llvm-svn: 127445

llvm-svn: 127434

llvm-svn: 127419

expand the testing of the narrowing shift right instructions.

No functionality change.

llvm-svn: 127193

llvm-svn: 126931

Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

llvm-svn: 126915

Intended to be atomic with clang r126828.

llvm-svn: 126827

llvm-svn: 126733

llvm-svn: 126731

shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723

   InstAlias<{alias}, {aliasee}>;

The InstAlias instruction should be able to go from the MCInst to the
{alias}. All of the information is there to match the MCInst with the
{aliasee}. From there, it's a simple matter to emit the {alias}, with the
correct operands from the {aliasee}.

The code this patch generates can be used by the InstPrinter to automatically
print out the alias without having to write special C++ code to handle the
situation.

This is a WIP, and therefore are several limitations. For instance, it cannot
handle AsmOperands at the moment. It also doesn't know what to do when two
{alias}es match the same {aliasee}. (Currently, it just ignores those two cases
and allows the printInstruction method to handle them.)

llvm-svn: 126538

llvm-svn: 126436

Patch by Jai Menon.

llvm-svn: 126165

Requires CMake 2.8.3 or newer.

llvm-svn: 126092

llvm-svn: 125969

Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for fixed-length instruction encodings.
A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks
provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen
like the existing disassembly emitters do.

The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove
some of the hacks the old one introduced to tblgen.

llvm-svn: 125966

llvm-svn: 125792

Patch thanks to Zach Anderson.

llvm-svn: 125721

-Use the tablegen class name for the checker class name.
-Mark checker packages as hidden/not hidden.

llvm-svn: 125558

llvm-svn: 125493

- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
  from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
  wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.

llvm-svn: 125489

llvm-svn: 125452