into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686

For disassembly only.

A8.6.300

llvm-svn: 95669

llvm-svn: 95609

llvm-svn: 95603

The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.

A8.6.295

llvm-svn: 95584

llvm-svn: 95560

A8.6.331 VMOV (between two ARM core registers and two single-precision registers)

llvm-svn: 95548

Radar 7614112.

llvm-svn: 95456

llvm-svn: 95397

of const ones.  non-const ones aren't very useful, because you can't
even, say, emit them.

llvm-svn: 95205

llvm-svn: 95181

the end of the instruction instead of expecting the caller to
do it.  This currently causes the asm-verbose instruction 
comments to be on the next line.

llvm-svn: 95178

than DEBUG_VALUE :(  ) into the target indep AsmPrinter.cpp
file.   This allows elimination of the 
NO_ASM_WRITER_BOILERPLATE hack among other things.

llvm-svn: 95177

even when -disable-fp-elim is specified.

llvm-svn: 95161

llvm-svn: 95160

mccontext instead of having AsmPrinter do it.  This allows other 
types of MCStreamer's to be passed in.

llvm-svn: 95155

llvm-svn: 95146

llvm-svn: 95138

llvm-svn: 95134

eliminate random "code emitter" stuff in Alpha, except for
the JIT path.  Next up, remove the template cruft.

llvm-svn: 95131

llvm-svn: 95130

llvm-svn: 95112

Rn operand.

llvm-svn: 95025

llvm-svn: 94955

Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).

Allow unaligned memops on darwin and conservatively disallow them otherwise.

llvm-svn: 94889

bit (Inst{22}) and the M bit (Inst{5}) should be left unspecified.  For binary
format instructions, Inst{6} and Inst{4} need to specified for proper decodings.

llvm-svn: 94855

runOnMachineFunction, and switch PPC to use EmitFunctionBody.
The two ppc asmprinters now don't heave to define 
runOnMachineFunction.

llvm-svn: 94722

llvm-svn: 94719

Move the X86 implementation of function body emission up to 
AsmPrinter::EmitFunctionBody, which works by calling the virtual
EmitInstruction method.

llvm-svn: 94716

Overload it in the ARM backend to do nothing, since is does insane
constant pool emission.

llvm-svn: 94708

llvm-svn: 94703

MachineFunction::Alignment instead.

llvm-svn: 94701

Modules and ModuleProviders. Because the "ModuleProvider" simply materializes
GlobalValues now, and doesn't provide modules, it's renamed to
"GVMaterializer". Code that used to need a ModuleProvider to materialize
Functions can now materialize the Functions directly. Functions no longer use a
magic linkage to record that they're materializable; they simply ask the
GVMaterializer.

Because the C ABI must never change, we can't remove LLVMModuleProviderRef or
the functions that refer to it. Instead, because Module now exposes the same
functionality ModuleProvider used to, we store a Module* in any
LLVMModuleProviderRef and translate in the wrapper methods.  The bindings to
other languages still use the ModuleProvider concept.  It would probably be
worth some time to update them to follow the C++ more closely, but I don't
intend to do it.

Fixes http://llvm.org/PR5737 and http://llvm.org/PR5735.

llvm-svn: 94686

llvm-svn: 94627

Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.

llvm-svn: 94626

llvm-svn: 94612

Default HasSetDirective to true, since most targets have it.

The targets that claim to not have it probably do, or it is
spelled differently. These include Blackfin, Mips, Alpha, and
PIC16.  All of these except pic16 are normal ELF targets, so
they almost certainly have it.

llvm-svn: 94585

Original patch by Sandeep Patel and updated by me.

llvm-svn: 94582

llvm-svn: 94580