it builds OK on Visual Studio.

llvm-svn: 95702

It fails with a release build only, for reasons
as yet unknown.  (If there's a better way to Xfail
things here let me know, doesn't seem to be any
prior art in unittests.)

llvm-svn: 95700

llvm-svn: 95699

out of the AsmWriterEmitter.  This patch does the physical
code movement, but leaves the implementation unchanged. I'll
make any changes necessary to generalize the code in a
separate patch.

llvm-svn: 95697

in X86-32 mode.  This is still required in x86-64 mode to avoid
forming [disp+rip] encoding.  Rewrite the SIB byte decision logic
to be actually understandable.

llvm-svn: 95693

enable constant 0 offset lowering.

llvm-svn: 95691

a confusing idiom to check for ESP or RSP.

llvm-svn: 95690

llvm-svn: 95689

llvm-svn: 95688

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686

Thanks to Jochen Wilhelmy for the suggestion!

llvm-svn: 95677

consuming for a simple optimization.

llvm-svn: 95671

llvm-svn: 95670

For disassembly only.

A8.6.300

llvm-svn: 95669

Patch by M Wahab!

llvm-svn: 95668

llvm-svn: 95667

is done for getTripCount.

llvm-svn: 95666

llvm-svn: 95665

and remove a few old and unreduced ones.  Fixes PR5624. 

llvm-svn: 95656

llvm-svn: 95655

llvm-svn: 95654

llvm-svn: 95653

llvm-svn: 95652

llvm-svn: 95651

llvm-svn: 95650

llvm-svn: 95649

llvm-svn: 95647

llvm-svn: 95646

whitespace tokens in the right places.

llvm-svn: 95645

Peter Hawkins!

llvm-svn: 95644

llvm-svn: 95643

xform.

llvm-svn: 95642

llvm-svn: 95641

library was reporting inaccurate token IDs.

llvm-svn: 95639

	movl	$3735928559, a          ## inst: <MCInst 1273 <MCOperand Reg:0> <MCOperand Imm:1> <MCOperand Reg:0> <MCOperand Expr:(a)> <MCOperand Reg:0> <MCOperand Expr:(3735928559)>>

after:

	movl	$3735928559, a          ## <MCInst #1273
                                        ##   <MCOperand Reg:0>
                                        ##   <MCOperand Imm:1>
                                        ##   <MCOperand Reg:0>
                                        ##   <MCOperand Expr:(a)>
                                        ##   <MCOperand Reg:0>
                                        ##   <MCOperand Expr:(3735928559)>>

llvm-svn: 95637

Previously spill registers, whose def indexes are not defined, would sometimes be improperly marked as coalescable with conflicting registers. The new findCoalesces routine conservatively assumes that any register with at least one undefined def is not coalescable with any register it interferes with.

llvm-svn: 95636

llvm-svn: 95634

Added copy sensible construction & assignment to PBQP graphs and fixed a memory access bug in the heuristic solver.

llvm-svn: 95633

llvm-svn: 95632