Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.

llvm-svn: 192567

Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.

llvm-svn: 192566

Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.

llvm-svn: 192565

Don't use 64-bit versions of MOVMSKPD in CodeGen. The instructions only produce a 1-bit result so we can just use SUBREG_TO_REG to extend the 32-bit versions.

llvm-svn: 192562

llvm-svn: 192557

llvm-svn: 192556

llvm-svn: 192555

llvm-svn: 192554

llvm-svn: 192553

It makes apparently no change it to set this bit or not but the
docs recommand to left it cleared.

llvm-svn: 192552

llvm-svn: 192525

Patch by: Jay Cornwall

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 192523

llvm-svn: 192522

they can be better handled and optimized in the Mips16 constant island code.

llvm-svn: 192520

llvm-svn: 192519

llvm-svn: 192499

This doesn't change the meaning of the output, but makes look right. PR17539.

llvm-svn: 192483

llvm-svn: 192458

llvm-svn: 192451

llvm-svn: 192450

llvm-svn: 192449

INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. 
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
 general purpose register. The changes to parseMSARegs reflect that requirement.

llvm-svn: 192447

[NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc

Fixes PR17529

llvm-svn: 192445

Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom comments for implicit defs

For NVPTX, this fixes a crash where the emitImplicitDef implementation was expecting physical registers,
while NVPTX uses virtual registers (with a couple of exceptions).  Now, the implicit def comment will be
emitted as a true PTX register name. Other targets can use this to customize the output of implicit def
comments.

Fixes PR17519

llvm-svn: 192444

[mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics)

llvm-svn: 192438

llvm-svn: 192435

llvm-svn: 192434

llvm-svn: 192433

When a ConstantExpr which uses a thread local is part of a PHI node
instruction, the insruction that replaces the ConstantExpr must
be inserted in the predecessor block, in front of the terminator instruction.
If the predecessor block has multiple successors, the edge is first split.

llvm-svn: 192432

llvm-svn: 192431

llvm-svn: 192430

[mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics)

llvm-svn: 192429

llvm-svn: 192410

llvm-svn: 192406

llvm-svn: 192375

The function is used by the machine verifier and checks that VOP*
instructions have legal operands.

llvm-svn: 192367

During instruction selection, we rewrite the destination register
class for MIMG instructions based on their writemasks.  This creates
machine verifier errors since the new register class does not match
the register class in the MIMG instruction definition.

We can avoid this by defining different MIMG instructions for each
possible destination type and then switching to the correct instruction
when we change the register class.

llvm-svn: 192365

This prevents the machine verifier from complaining about uses of
an undefined physical register.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 192364

StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of
shader from shadertoy (which exhibits complex control flow constructs) to works
correctly with respect to CFG handling (and allow us to detect potential bug in
other part of the backend).

We provide a cmd line argument to disable the pass for debug purpose.

Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 192363

Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192361