Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.

llvm-svn: 192567

llvm-svn: 192525

llvm-svn: 192522

llvm-svn: 192519

llvm-svn: 192425

llvm-svn: 192339

llvm-svn: 192279

llvm-svn: 192275

Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building.

llvm-svn: 192175

Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.

llvm-svn: 192171

Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.

llvm-svn: 192090

llvm-svn: 192086

Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon.

llvm-svn: 192026

llvm-svn: 191941

Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon.

llvm-svn: 191940

llvm-svn: 191874

This is useful for some ARM intrinsics such as VCVTN which does a <4 x float> <-> <4 x half> conversion.

llvm-svn: 191870

Patch by Alp Toker.

llvm-svn: 191757

The old code skipped one of the sorting criteria if either pattern had
no types.  This could lead to cycles of the form X < Y, Y < Z, Z < X.

llvm-svn: 191735

Filter out repeated sections from the X86 disassembler modRMTable. Saves about ~43K from a released build. Unfortunately the disassembler tables are still upwards of 800K.

llvm-svn: 191652

Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.

llvm-svn: 191649

Ideally, the machinel model is added at the time the instructions are
defined. But many instructions in X86InstrSSE.td still need a model.

Without this workaround the scheduler asserts because x86 already has
itinerary classes for these instructions, indicating they should be
modeled by the scheduler. Since we use the new machine model for other
instructions, it expects a new machine model for these too.

llvm-svn: 191391

llvm-svn: 191356

llvm-svn: 191355

llvm-svn: 191280

Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.

llvm-svn: 191263

Add missing index comments to the left side of the DAG ISel matcher table for each individual case of SwitchOpcode/Type.

llvm-svn: 191181

This makes using array_pod_sort significantly safer. The implementation relies
on function pointer casting but that should be safe as we're dealing with void*
here.

llvm-svn: 191175

libc++ didn't seem to like a non-const call operator.

llvm-svn: 190797

TableGen was sorting the entries in some of its internal data
structures by pointer. This order filtered through to the final
matching table and affected the diagnostics produced on bad assembly
occasionally.

It also turns out STL algorithms are ridiculously easy to misuse on
containers with custom order methods. (No bugs before, or now that I
know of, but plenty in the middle).

This should fix the sanitizer bot, which ends up with weird pointers.

llvm-svn: 190793

llvm-svn: 190792

llvm-svn: 190770

The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.

The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
  ComplexDeprecationPredicate<"MCR">

would mean you would have to define the following function:
  bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
                             std::string &Info)

Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.

The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.

llvm-svn: 190598

Cuts down the bloat in the AArch64 asm writer a bit.

llvm-svn: 190527

Otherwise SequenceToOffsetTable will sort by pointer and becomes non-deterministic.

llvm-svn: 190514

llvm-svn: 189839

llvm-svn: 189618

llvm-svn: 189617

llvm-svn: 189567

Re-submitting r189416 with fix for Windows build on where strcasecmp is not defined.

llvm-svn: 189501