llvm-svn: 30946

llvm-svn: 29096

llvm-svn: 28889

magic to work.

llvm-svn: 28847

llvm-svn: 28102

llvm-svn: 26806

llvm-svn: 26800

llvm-svn: 26562

llvm-svn: 25916

llvm-svn: 25914

Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place.  Other methods should also be moved if anyoneis interested. :)

llvm-svn: 25913

llvm-svn: 23813

purely mechanical.

llvm-svn: 23778

redundant after the change.

llvm-svn: 23759

This completes the grand PPC file renaming

llvm-svn: 23745

llvm-svn: 23743

llvm-svn: 23738

classes on PPC.  We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced.  This fixes Regression/CodeGen/PowerPC/fpcopy.ll

llvm-svn: 23654

These are used to represent float and double values, and the two regclasses
contain the same physical registers.

llvm-svn: 23577

is zero.  This lets the register allocator elide some copies in some cases.

This implements CodeGen/PowerPC/rlwimi-commute.ll

llvm-svn: 23292

llvm-svn: 21425

llvm-svn: 21246

loading a 32bit constant into a register whose low halfword is all zeroes.

We now omit the ori after the lis for the following C code:

int bar(int y) { return y * 0x00F0000; }

_bar:
.LBB_bar_0:     ; entry
        ; IMPLICIT_DEF
        lis r2, 15
        mullw r3, r3, r2
        blr

llvm-svn: 16825

llvm-svn: 15850

llvm-svn: 15671

llvm-svn: 15631

  addi r1, r2, 0
  addi r1, <frame index #n>, 0

so we must check for the second parameter being a register for this instruction
to be considered a reg-to-reg copy.

llvm-svn: 15244

llvm-svn: 15243

* List formats of instructions currently recognized as moves

llvm-svn: 15242

llvm-svn: 14899

llvm-svn: 14898

llvm-svn: 14283

llvm-svn: 11987

llvm-svn: 11984

llvm-svn: 11828