Add some special purpose register definitions to the MBlaze backend and cleanup some old, unused floating point register definitions.

llvm-svn: 121882

llvm-svn: 121880

llvm-svn: 121878

 * mergeIn now uses constant folding for constants that are provably not-equal.
 * sink some sanity checks from the get*() methods into the mark*() methods, to ensure that we never have a constant/notconstant ConstantInt
 * some textual cleanups, whitespace changes, removing "else" after return, that sort of thing.

llvm-svn: 121877

rdar://8768390

llvm-svn: 121876

llvm-svn: 121875

llvm-svn: 121872

Bypass loops have the current live range live through, but contain no uses or
defs. Splitting around a bypass loop can free registers for other uses inside
the loop by spilling the split range.

llvm-svn: 121871

This method returns the set of loops with uses that are candidates for
splitting.

llvm-svn: 121870

instcombine and into InstructionSimplify.

llvm-svn: 121861

it to be replaced by undef rather than not replaced at all, the idea being that
this may reduce the amount of work done by whoever called InstructionSimplify.

llvm-svn: 121860

Teach jump threading to "look through" a select when the branch direction of a terminator depends on it.
When it sees a promising select it now tries to figure out whether the condition of the select is known in any of the predecessors and if so it maps the operands appropriately.

llvm-svn: 121859

llvm-svn: 121858

With this we don't need the EffectiveSize field anymore. Without that field
LayoutFragment only updates offsets and we don't need to invalidate the
current fragment when it is relaxed (only the ones following it).

This is also a very small improvement in the accuracy of the layout info as
we now use the after relaxation size immediately.

llvm-svn: 121857

Since we now don't update addresses so early, we might relax a bit more than
we need to. This is simillar to the issue in PR8467.

llvm-svn: 121856

llvm-svn: 121854

llvm-svn: 121853

llvm-svn: 121851

llvm-svn: 121850

llvm-svn: 121849

a wider mul if the wider mul is legal.

llvm-svn: 121848

result, the top bits are truncated off anyway, just use SRL.

llvm-svn: 121846

llvm-svn: 121838

llvm-svn: 121820

immediate versions.

llvm-svn: 121819

this case involve a select that simplifies to itself.

llvm-svn: 121817

llvm-svn: 121816

llvm-svn: 121815

llvm-svn: 121812

llvm-svn: 121809

particular, we want

   ldr r2, [r3]

to be equivalent to

   ldr r2, [r3, #0]

and not

   ldr r2, [r3, r0]

llvm-svn: 121808

llvm-svn: 121807

llvm-svn: 121806

llvm-svn: 121805

llvm-svn: 121801

llvm-svn: 121798

llvm-svn: 121797

is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.

llvm-svn: 121794

regB = move RCX
regA = op regB, regC
RAX  = move regA
where both regB and regC are killed. If regB is constrainted to non-compatible
physical registers but regC is not constrainted at all, then it's better to
commute the instruction.
       movl    %edi, %eax
       shlq    $32, %rcx
       leaq    (%rcx,%rax), %rax
=>
       movl    %edi, %eax
       shlq    $32, %rcx
       orq     %rcx, %rax
rdar://8762995

llvm-svn: 121793

llvm-svn: 121792