llvm-svn: 158164

Match expectations of the new latency API. Cleanup and make the logic consistent.

llvm-svn: 158163

llvm-svn: 158162

llvm-svn: 158161

It will cause assertion failure later on.

llvm-svn: 158160

Fixes pr13048.

llvm-svn: 158158

Move terminator machine verification to check MachineBasicBlock::instr_iterator instead of MBB::iterator

llvm-svn: 158154

This patch will optimize the following
    movq    %rdi, %rax
    subq    %rsi, %rax
    cmovsq  %rsi, %rdi
    movq    %rdi, %rax
to
    cmpq    %rsi, %rdi
    cmovsq  %rsi, %rdi
    movq    %rdi, %rax

Perform this optimization if the actual result of SUB is not used.

rdar: 11540023
llvm-svn: 158126

The commit is intended to fix rdar://11540023.
It is implemented as part of peephole optimization. We can actually implement
this in the SelectionDAG lowering phase.

llvm-svn: 158122

Bundles should be treated as one atomic transaction when checking
liveness. That is how the register allocator (and VLIW targets) treats
bundles.

llvm-svn: 158116

LLVM should be -Wunused-private-field clean now.

llvm-svn: 158103

Allow targets to access this API. It's required for RegisterPressure.

llvm-svn: 158102

Make it a general utility for use by Targets.

llvm-svn: 158097

LLVM is now -Wunused-private-field clean except for
- lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields.
- gtest.

llvm-svn: 158096

There are some that I didn't remove this round because they looked like
obvious stubs. There are dead variables in gtest too, they should be
fixed upstream.

llvm-svn: 158090

X86.
rdar://11496434

llvm-svn: 158087

matter.
rdar://11579835

llvm-svn: 158084

Remat has been stable for years, and it isn't done by
LiveIntervalAnalysis any longer. (See LiveRangeEdit).

llvm-svn: 158079

instructions to reoptimize.  Exploit this to more systematically eliminate
dead instructions (this isn't very useful in practice but is convenient for
analysing some testcase I am working on).  No need for WeakVH any more: use
an AssertingVH instead.

llvm-svn: 158073

llvm-svn: 158069

llvm-svn: 158055

llvm-svn: 158049

It is useful outside RegAllocBase.

llvm-svn: 158041

Soon we'll be making LiveIntervalUnions for register units as well.

This was the only place using the RepReg member, so just remove it.

llvm-svn: 158038

llvm-svn: 158037

Don't print out the register number and spill weight, making the TRI
argument unnecessary.

This allows callers to interpret the reg field. It can currently be a
virtual register, a physical register, a spill slot, or a register unit.

llvm-svn: 158031

Instead of computing a live interval per physreg, LiveIntervals can
compute live intervals per register unit. This makes impossible the
confusing situation where aliasing registers could have overlapping live
intervals. It should also make fixed interferernce checking cheaper
since registers have fewer register units than aliases.

Live intervals for regunits are computed on demand, using MRI use-def
chains and the new LiveRangeCalc class. Only regunits live in to ABI
blocks are precomputed during LiveIntervals::runOnMachineFunction().

The regunit liveness computations don't depend on LiveVariables.

llvm-svn: 158029

These LiveRangeCalc methods are to be used when computing a live range
from scratch.

llvm-svn: 158027

Patch by Ivan Llopard.

llvm-svn: 158025

Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.

llvm-svn: 158021

expression (a * b + c) that can be implemented as a fused multiply-add (fma)
if the target determines that this will be more efficient. This intrinsic
will be used to implement FP_CONTRACT support and an aggressive FMA formation
mode.

If your target has a fast FMA instruction you should override the
isFMAFasterThanMulAndAdd method in TargetLowering to return true.

llvm-svn: 158014

llvm-svn: 158013

llvm-svn: 158007

llvm-svn: 158004

llvm-svn: 157981

llvm-svn: 157980

This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.

llvm-svn: 157979

Use ILP heuristics for long latency instrs if no scoreboard exists.

llvm-svn: 157978

valid itinerary but no pipeline stages.

An itinerary can contain useful scheduling information without specifying pipeline stages for each instruction.

llvm-svn: 157977

llvm-svn: 157976