[L]oad, [u]se, [d]ef, or [S]tore slots.

This makes it easier to see if two indices refer to the same instruction,
avoiding mental mod 4 calculations.

llvm-svn: 106766

which trivially fold away.

llvm-svn: 106765

Also keep track of the original DstREg before subregister adjustments.

llvm-svn: 106753

In this case it is essential that the kill is real because the spiller will
decide to omit a spill if it thinks there is a later kill.

llvm-svn: 106751

as many tests as possible.

llvm-svn: 106749

when the condition is constant. This optimization shouldn't be
necessary, because codegen shouldn't be able to find dead control
paths that the IR-level optimizer can't find. And it's undesirable,
because it encourages bugpoint to leave "br i1 false" branches
in its output. And it wasn't updating the CFG.

I updated all the tests I could, but some tests are too reduced
and I wasn't able to meaningfully preserve them.

llvm-svn: 106748

llvm-svn: 106746

case where the bit mask has exactly one bit.

llvm-svn: 106716

Whiny buildbots.

llvm-svn: 106710

CoalescerPair can determine if a copy can be coalesced, and which register gets
merged away. The old logic in SimpleRegisterCoalescing had evolved into
something a bit too convoluted.

llvm-svn: 106701

into the same node, but with different non-memory operands, we need to replace
the memory operands after it's finished morphing.

llvm-svn: 106643

Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.

llvm-svn: 106634

atomic intrinsics, either because the use locking instructions for the
atomics, or because they perform the locking directly. Add support in the
DAG combiner to fold away the fences.

llvm-svn: 106630

llvm-svn: 106627

Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang.

Conflicts:

	lib/CodeGen/MachineSink.cpp

llvm-svn: 106614

instructions.

This does not affect codegen much because SUBREG_TO_REG is only used by X86 and
X86 does not use the register scavenger, but it prevents verifier errors.

llvm-svn: 106583

into a utility routine, teach it how to update MachineLoopInfo, and
make use of it in MachineLICM to split critical edges on demand.

llvm-svn: 106555

Measurements show that it does not speed up coalescing, so there is no reason
the keep the added complexity around.

Also clean out some unused methods and static functions.

llvm-svn: 106548

llvm-svn: 106542

kill and dead flags will end up on.

llvm-svn: 106520

getNamedMetadata().

llvm-svn: 106518

llvm-svn: 106517

llvm-svn: 106516

llvm-svn: 106515

in addition to the kill flags.

llvm-svn: 106512

opportunities. For example, this lets it emit this:

   movq (%rax), %rcx
   addq %rdx, %rcx

instead of this:

   movq %rdx, %rcx
   addq (%rax), %rcx

in the case where %rdx has subsequent uses. It's the same number
of instructions, and usually the same encoding size on x86, but
it appears faster, and in general, it may allow better scheduling
for the load.

llvm-svn: 106493

SmallVector, and other SmallVector simplifications.

llvm-svn: 106452

llvm-svn: 106423

Split the code for materializing a value out of
SelectionDAGBuilder::getValue into a helper function, so that it can
be used in other ways. Add a new getNonRegisterValue function which
uses it, for use in code which doesn't want a CopyFromReg even
when FuncMap.ValueMap already has an entry for it.

llvm-svn: 106422

llvm-svn: 106415

the LocalValueMap, to make it more flexible when fast-isel isn't
proceding straight top-down.

llvm-svn: 106414

llvm-svn: 106383

on calls and similar instructions.

llvm-svn: 106353

the inserted INSERT_SUBREGs after us.

llvm-svn: 106345

- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.

llvm-svn: 106344

llvm-svn: 106342

instructions, but it doesn't really understand live ranges, so the first
INSERT_SUBREG uses an implicitly defined register.

Fix it in LiveVariableAnalysis by adding the <undef> flag.

llvm-svn: 106333

llvm-svn: 106330

llvm-svn: 106324

Teach iff-converter to properly count # of dups. It was not skipping over dbg_value's which resulted in non-duplicated instructions being deleted. rdar://8104384.

llvm-svn: 106323