of r146334!

llvm-svn: 146338

llvm-svn: 146335

the only parts of TM that depends on CodeGen headers with it.

llvm-svn: 146334

Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.

llvm-svn: 146328

Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.

llvm-svn: 146322

Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.

llvm-svn: 146318

The split point is picked such that the newly created water has the same
alignment as the function. This makes the island suitable for constant
pool entries with potentially higher alignment.

This also fixes an issue where the basic block was split one instruction
too late, causing nonconvergence of the algorithm.

<rdar://problem/10550705>

There is still an issue with correctly packing differently aligned
entries in the island.

llvm-svn: 146314

llvm-svn: 146313

does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.

llvm-svn: 146311

llvm-svn: 146300

llvm-svn: 146299

llvm-svn: 146296

Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.

llvm-svn: 146285

When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057

llvm-svn: 146283

llvm-svn: 146281

Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.

llvm-svn: 146278

llvm-svn: 146270

llvm-svn: 146267

llvm-svn: 146266

llvm-svn: 146264

llvm-svn: 146258

llvm-svn: 146257

llvm-svn: 146256

Move isUnpredicatedTerminator() default implementation to TargetInstrInfoImpl to break Target's dependency on CodeGen.

llvm-svn: 146247

llvm-svn: 146246

llvm-svn: 146232

specified.

llvm-svn: 146229

llvm-svn: 146201

llvm-svn: 146196

llvm-svn: 146194

Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can use the former to prevent the formation of libm SDNode's when  -fno-builtin is passed.

llvm-svn: 146193

llvm-svn: 146192

code looks pretty bad compared to SSE.

rdar://10538793

llvm-svn: 146191

For better 'gas' compatibility.

llvm-svn: 146185

MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.

llvm-svn: 146183

llvm-svn: 146182

Don't explicitly marked libm rounding ops as legal on SSE4.1/AVX.  There don't seem to be patterns for these, so I don't know why they were marked legal in the first place.
Fixes failures caused by r146171.

llvm-svn: 146180

llvm-svn: 146179

llvm-svn: 146177

- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.

llvm-svn: 146175