llvm-svn: 108991

llvm-svn: 108929

instruction selection to prefer it when possible. rdar://7903972

llvm-svn: 108844

llvm-svn: 108841

llvm-svn: 108812

llvm-svn: 108787

out of the AsmPrinter directory into libarm.  Now the
ARM InstPrinters depend jsut on the MC stuff, not on vmcore
or codegen.

llvm-svn: 108783

ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.

llvm-svn: 108761

it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR6581.

llvm-svn: 108730

llvm-svn: 108727

it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR7499.

llvm-svn: 108722

 - Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.

llvm-svn: 108664

instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.

llvm-svn: 108608

llvm-svn: 108603

llvm-svn: 108601

llvm-svn: 108588

stack realignment on ARM.

Also check for function attributes as we do on X86 as well as
make explicit that we're checking can as well as needs in this function.

llvm-svn: 108582

and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.

llvm-svn: 108570

llvm-svn: 108567

Thumb2ITBlockPass.

llvm-svn: 108564

thus is a much more meaningful name.

llvm-svn: 108563

-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.

llvm-svn: 108465

llvm-svn: 108396

instructions use different values (e.g., 2-byte or 4-byte alignment).
Also fix ARMInstPrinter to print these alignments as bits instead of bytes.

llvm-svn: 108386

llvm-svn: 108366

in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284

llvm-svn: 108339

Patch by Brian Lucas. PR7636.

llvm-svn: 108332

llvm-svn: 108328

llvm-svn: 108324

of the value of the immediate.

llvm-svn: 108323

Radar 7373643.

llvm-svn: 108303

NEON VMOV-immediate instructions.  This simplifies some things.

llvm-svn: 108275

Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.

llvm-svn: 108258

llvm-svn: 108256

avoid replicated code.

llvm-svn: 108227

instructions already have implicit defs of LR.  The comment suggests that
this is intended to fix something like pr6111, but it doesn't really do
that either.

llvm-svn: 108186

llvm-svn: 108130

The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

llvm-svn: 108099

llvm-svn: 108094

llvm-svn: 108078