llvm-svn: 110460

llvm-svn: 110410

ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396

llvm-svn: 109765

llvm-svn: 109045

threshold a bit per experimentation.

llvm-svn: 108935

loop, for the reasons in the comments.  This is a
major win on 253.perlbmk on ARM Darwin.  I expect it
to be a good heuristic in general, but it's possible
some things will regress; I'll be watching.
7940152.

llvm-svn: 108792

Teach ProcessImplicitDefs to transform more COPY instructions into IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620.

llvm-svn: 108304

intended functionality change.

The avoidance of hoistiing implicitdef seems wrong though.

llvm-svn: 108109

llvm-svn: 108001

into a utility routine, teach it how to update MachineLoopInfo, and
make use of it in MachineLICM to split critical edges on demand.

llvm-svn: 106555

llvm-svn: 105065

when they move instructions.

llvm-svn: 103737

register is not killed in the loop.

This fixes 188.ammp on ARM where the post-ra scheduler would grab a register
that looked available but wasn't.

A testcase would be huge and fragile, sorry.

llvm-svn: 101930

the live-in sets of BBs in the loop. Otherwise later pass may end up using the
registers and override the invariant. rdar://7852937
No reasonablly sized test case possible.

llvm-svn: 101626

llvm-svn: 101183

llvm-svn: 101170

Expand postra machine licm's capability a little more. If an instruction's register operands are all loop invariants, then it's safe to hoist it.

llvm-svn: 101167

Teach postra machine licm to hoist more obvious invariants, e.g. instructions with no source operands.

llvm-svn: 101154

MachineBasicBlock::livein_iterator a const_iterator, because
clients shouldn't ever be using the iterator interface to
mutate the livein set.

llvm-svn: 101147

llvm-svn: 101034

llvm-svn: 100858

llvm-svn: 100742

llvm-svn: 100610

llvm-svn: 100609

llvm-svn: 100592

- Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).

llvm-svn: 97628

llvm-svn: 97360

defs or uses. The regular def and use checking below covers them, and
can be more precise. It's safe to hoist an instruction with a dead
implicit def if the register isn't live into the loop header.

llvm-svn: 97352

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

Change errs() to dbgs().

llvm-svn: 92547

contains another loop, or an instruction. The loop form is
substantially more efficient on large loops than the typical
code it replaces.

llvm-svn: 91654

llvm-svn: 89510

llvm-svn: 89477

Fix debug code that assumes getBasicBlock never returns NULL.

llvm-svn: 89428

llvm-svn: 89129

  except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.

llvm-svn: 86328

llvm-svn: 86085

llvm-svn: 85947

llvm-svn: 85827