llvm-svn: 139485

Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.

llvm-svn: 139484

Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

llvm-svn: 139440

llvm-svn: 139432

llvm-svn: 139422

Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.

llvm-svn: 139415

llvm-svn: 139399

llvm-svn: 139397

llvm-svn: 139396

llvm-svn: 139395

llvm-svn: 139393

llvm-svn: 139392

llvm-svn: 139391

llvm-svn: 139390

llvm-svn: 139389

llvm-svn: 139386

llvm-svn: 139385

llvm-svn: 139381

llvm-svn: 139371

llvm-svn: 139356

llvm-svn: 139328

Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322

without a base symbol that must not have a relocation entry.

llvm-svn: 139316

llvm-svn: 139292

More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

llvm-svn: 139272

Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

llvm-svn: 139270

llvm-svn: 139267

llvm-svn: 139266

llvm-svn: 139264

llvm-svn: 139258

Need branch relocation support to distinguish this encoding from the
16-bit Thumb1 encoding w/o the explicit .w suffix. That comes later, though.

llvm-svn: 139257

llvm-svn: 139256

llvm-svn: 139255

llvm-svn: 139251

Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.

llvm-svn: 139250

llvm-svn: 139244

Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.

llvm-svn: 139242

llvm-svn: 139240

llvm-svn: 139200

llvm-svn: 139199