llvm-svn: 113653

iterator when an optimization took place. This allows us to do more insane
things with the code than just remove an instruction or two.

llvm-svn: 113640

llvm-svn: 113632

llvm-svn: 113614

take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.

llvm-svn: 113570

llvm-svn: 113386

LiveIntervals already adds <imp-def> operands for super-registers when a subreg
def defines the whole register. Thus, it is not necessary to do it again when
rewriting.

In fact, the super-register imp-defs caused miscompilations because the late
scheduler couldn't see that the super-register was read.

We still add super-reg <imp-use,kill> operands when rewriting virtuals to
physicals.

llvm-svn: 113299

llvm-svn: 113117

llvm-svn: 113108

Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:

int foo(int x, int y, int z) {
  return x+y+z;
}

used to compile into:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	movl	4(%rsp), %esi
	addl	%edx, %esi
	movl	(%rsp), %edx
	addl	%esi, %edx
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Now we produce:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	addl	4(%rsp), %edx    ## Folded load
	addl	(%rsp), %edx     ## Folded load
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Fewer instructions and less register use = faster compiles.

llvm-svn: 113102

Clobber ranges are no longer used when joining physical registers.
Instead, all aliases are checked for interference.

llvm-svn: 113084

llvm-svn: 113073

overload UserInInstr. Explicitly check Allocatable. The early exit in the
condition will mean the performance impact of the extra test should be
minimal.

llvm-svn: 113016

solve the root problem, but it corrects the bug in the code I added to
support legalizing in the case where the non-extended type is also legal.

llvm-svn: 112997

slot.

Teach it to also check for early clobbered aliases, and early clobber operands
following the current operand.

This fixes the miscompilation in PR8044 where EC registers eax and ecx were
being used for inputs.

llvm-svn: 112988

Original commit message:
Use the SSAUpdator to turn calls to eh.exception that are not in a
landing pad into uses of registers rather than loads from a stack
slot.  Doesn't touch the 'orrible hack code - Bill needs to persuade
me harder :)

llvm-svn: 112952

Thanks Chris!

llvm-svn: 112900

llvm-svn: 112864

there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.

This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.

llvm-svn: 112861

llvm-svn: 112858

locally.

llvm-svn: 112845

llvm-svn: 112832

llvm-svn: 112830

Added support for register allocators to record which intervals are spill intervals, and where the uses and defs of the original intervals were in the original code.

Spill intervals can be hidden using the "-rmf-intervals=virt-nospills*" option.

llvm-svn: 112811

llvm-svn: 112809

llvm-svn: 112807

llvm-svn: 112787

at them since they'd end up in the register weights list. Tell it to stop
doing that.

llvm-svn: 112756

This caused a miscompilation in WebKit where %RAX had conflicting defs when
RemoveCopyByCommutingDef was commuting a %EAX use.

llvm-svn: 112751

llvm-svn: 112746

physical register in a register class. Make sure to assert if the register
class is empty.

llvm-svn: 112743

llvm-svn: 112742

r112728 did this for fast regalloc.

llvm-svn: 112741

llvm-svn: 112728

llvm-svn: 112726

self host errors on clang-x86-64.

llvm-svn: 112719

landing pad into uses of registers rather than loads from a stack
slot.  Doesn't touch the 'orrible hack code - Bill needs to persuade
me harder :)

llvm-svn: 112702

This patch was developed on top of original patch by Artur Pietrek.

llvm-svn: 112678

llvm-svn: 112659

Reserved registers are unpredictable, and are treated as always live by machine
DCE.

Allocatable registers are never reserved, and can be used for virtual registers.

Unreserved, unallocatable registers can not be used for virtual registers, but
otherwise behave like a normal allocatable register. Most targets only have
the flag register in this set.

llvm-svn: 112649